Increase task stack size for PD host command task to 512. The nominal
stack size is 328 / 384, which is pretty close to the edge.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: Ifdf04923b817c832cbb77ba7f61c06a560aec97d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217452
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change erase page size from 1kB to 2kB. The datasheet
specifies that the page size is 2kB.
This was causing occasional failures in flashrom because
flashrom only erases and writes pages where the flash
contents don't match the new binary.
BUG=none
BRANCH=factory-ryu-6212.B
TEST=Load onto samus_pd, and verify that flashrom
works successfully.
Also added console debugging to verify that the actual erase
page size is 2kB. I left the CONFIG_FLASH_ERASE_SIZE at 1024
and added the following code.
static int command_flash_is_erased(int argc, char **argv)
{
int offset = -1;
int size = CONFIG_FLASH_ERASE_SIZE;
int rv;
rv = parse_offset_size(argc, argv, 1, &offset, &size);
if (rv)
return rv;
ccprintf("Offset %d, size %d, is erased: %d\n", offset, size,
flash_is_erased(offset, size));
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(flashiserased, command_flash_is_erased,
"",
"",
NULL);
Then:
> flashiserased 2048
Offset 2048, size 1024, is erased: 0
> flashiserased 3072
Offset 3072, size 1024, is erased: 0
> flashiserased 4096
Offset 4096, size 1024, is erased: 0
> flasherase 2048
Erasing 1024 bytes at 0x800...
> flashiserased 2048
Offset 2048, size 1024, is erased: 1
> flashiserased 3072
Offset 3072, size 1024, is erased: 1
> flashiserased 4096
Offset 4096, size 1024, is erased: 0
You can see when it tries to erase 1kB at 2048, it actually erases
2kB.
Change-Id: I02772d4671784930765df63fa99968a07b15882e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217475
Reviewed-by: Vic Yang <victoryang@chromium.org>
CL provides some useful information similar to the EC console command
'pd state <port>' when host command 'usbpd <port>' is sent from host
with no additional arguments.
Also added a few build asserts for role & mux strings.
BRANCH=none
BUG=chrome-os-partner:31690
TEST=manual
ectool --interface=lpc --dev=1 usbpd 1
Port C1 is enabled. Role:SNK Polarity:CC1 State:6
# has zinger attached
ectool --interface=lpc --dev=1 usbpd 0
Port C0 is enabled. Role:SNK Polarity:CC1 State:2
Change-Id: Id44eb7bf6a6fcfa888a0008a2249601967c50bcc
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217138
Reviewed-by: Alec Berg <alecaberg@chromium.org>
PD accessories that are RW update-able will broadcast their rw_hash
SHA1 digest upon connection to the PD MCU which will store it.
For update purposes, the host needs that accessories device id and
rw_hash to determine its proper firmware update payload.
This CL creates a host command that requests the type-C accessory info
attached to a particular port. It also implements an ectool command
to expose the host command.
BRANCH=none
BUG=chrome-os-partner:31361
TEST=manual,
# connect zinger to port 1 on samus
ectool --dev=1 --interface=lpc infopddev 1
Port:0 Device:1 Hash: 0x7f4d7a13 0xf07b65b9 0x41181e10 0xb99b3d5f 0x9dee1206
ectool --dev=1 --interface=lpc infopddev 0
Port:0 has no valid device
Also do the same on port 0 with similar results.
Change-Id: Id63c7edad77a43d43c14d8cd6bd96e08d0d9b501
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216814
Reviewed-by: Alec Berg <alecaberg@chromium.org>
PD accessories that are RW update-able will broadcast their rw_hash
SHA1 digest upon connection and remain in RO briefly for a response.
In order to speed-up the response and decouple common case of
accessory is up-to-date, the PD MCU will keep a small 4 entry table of
PD accessory device ids and their corresponding RW hashes for quick
lookup.
The AP will be the source of new updates and their corresponding
device id's and RW hashes and therefore needs a method to update the
PD MCU table.
This CL creates the table, host command & ectool command to facilitate
future driver / daemon to update the RW hash entries.
BRANCH=none
BUG=chrome-os-partner:31361
TEST=manual,
# from AP
for i in `seq 1 8` ; do
ectool --dev=1 --interface=lpc rwhashpd $i $i $i $i $i $i
done
# from samus_pd console
pd rwhash
Device:5 Hash: 0x00000005 0x00000005 0x00000005 0x00000005 0x00000005
Device:6 Hash: 0x00000006 0x00000006 0x00000006 0x00000006 0x00000006
Device:7 Hash: 0x00000007 0x00000007 0x00000007 0x00000007 0x00000007
Device:8 Hash: 0x00000008 0x00000008 0x00000008 0x00000008 0x00000008
Change-Id: Ibe87b3594793cd5215eba42160489b26974aadbc
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214366
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Whenever we're sending raw status bytes from the EC(while the we're not DMAing)
the bytes kinda get garbled, and not get sent in the right order. Sometimes we
want the last byte sent to keep repeating, the problem is that it doesn't.
Seems like the tx fifo doesn't play nice with the DMA. The way we fix this is by
sending bytes 4 times, effectively bypassing the TX fifo.
Protocol v2 was not fixed yet. It just displays a warning if one tries to use it
on F0.
BUG=chrome-os-partner:31390
BRANCH=None
TEST=ectool version should work in the most recent kernel(with the v3 protocol
version). spidev/python "s.transfer("\xdc\x02\x00\xde"+"\x00"*100)" should
return a deterministic packet(the only variation between calls should be the
number of \xfa recieved(40 vs 41 or so)).
"flashrom -p ec -l /tmp/layout.txt -i rw:/tmp/rw.bin -w -V" now works properly.
Change-Id: Ia2772277428bd45013f5721a6bedab13d0591423
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217083
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Fix for plankton v2 so that the VBUS voltage selection buttons
work properly (5V, 12V, and 20V).
BUG=none
BRANCH=none
TEST=load onto plankton v2, connect type-C to samus, and press
5V, 12V, and 20V buttons. read adc on samus side to verify it
is getting the proper voltage.
Change-Id: I5004675bf658834219c295292c669182af7d8393
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217258
Reviewed-by: Vic Yang <victoryang@chromium.org>
Add setting of new GPIO, prog_en, to flash_ec to be able to program
new plankton boards. This pin must be on for boot0 and nrst to be
connected from the FTDI to the MCU.
BUG=chrome-os-partner:31633
BRANCH=none
TEST=manual,
sudo servod -c plankton.xml
util/flash_ec --board=plankton
CQ-DEPEND=CL:216160
Change-Id: I29f882856e24147a7af283c5e82298c7736b8662
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216161
Reviewed-by: Todd Broch <tbroch@chromium.org>
This ensures that nothing previously flashed to the baord can
interfere with the flashing operation (by wedging the MCU or
putting it into a state that the falshing code can't handle).
This also adds a dependency on ec.bin to the flash
target, ensuring that the firmware image is up to date
when flashing.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=none
TEST=make buildall -j
Change-Id: I8cdfa6f5c84ed84d6b6e6b30d6683a23087f2c63
Reviewed-on: https://chromium-review.googlesource.com/215991
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Add checking the return value of enabling vbus in SRC_DISCONNECTED.
If failed to enable vbus, don't transition to SRC_DISCOVERY. This
can happen on zinger if zinger is in a fault condition, but once
the fault is cleared, we need to be in SRC_DISCONNECTED in order
to re-apply vbus.
BUG=none
BRANCH=none
TEST=load onto EVT zinger. without this change, if zinger is plugged
into a samus without a battery, when PD MCU is reset, zinger gets
stuck in SRC_DISCOVERY with vbus disabled because
pd_set_power_supply_ready() returns an error. This means to get
power back to samus, we need to unplug and replug raiden. This change
fixes the problem.
Change-Id: I2ac75c7095b5d819b54b2f25ec974ccfd974e1e2
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216608
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change USB_MCU_RST gpio used to reset PD MCU to push-pull instead
of open drain.
BUG=none
BRANCH=none
TEST=tested on EVT samus by using gpioget/gpioset to make sure
we can actually reset the PD MCU from the EC.
Change-Id: Id8460fdb32bc32d0dd4c236f3050d241312dce23
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216607
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
We switched which spi bus we were using for each type-C port EVT,
but missed one place where the busses should have been switched.
Note, this bug wasn't actually causing any problems because
we enable both spi busses at init time and they remain enabled.
BUG=none
BRANCH=none
TEST=load on EVT samus, make sure PD negotiation works on both
ports
Change-Id: I7b4fbee01b58be41521745d7bef6d9357e50be57
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216606
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This was inverted in the schematic, but is also connected to a FET
and is expected to be driven. However it is not working properly so
for now leave the GPIO as an input.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=build and boot on samus EVT
Change-Id: I10d6a40b1102df866a9d32c52a9f67eb24c3ce7a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216942
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When RTCRST is asserted the PCH is not able to sequence properly
right away. In testing 5ms was usually suitable but to be safe a
10ms delay is added.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=esc+refresh+power on samus EVT boots to recovery
Change-Id: I10045fe56e107e853ff297bd83ea5369c44a2020
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216941
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This GPIO was reassigned and needs to be reflected properly. Since
it no longer exists we must also disable CONFIG_SWITCH_DEDICATED_RECOVERY
so it is not sampled to determine recovery state.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=boot on samus EVT in non-recovery mode
Change-Id: I6e3b19956e4c8075a3f5cd4ec7e16bea934b1e98
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216940
Reviewed-by: Alec Berg <alecaberg@chromium.org>
- Added LID_CLOSED_L and BASE_PRESET_L to PA2/PA3.
- Moved UART_TX/RX to PA9/PA10 (UART 1)
- Change DMA mapping to keep using DMA 4,5 for UART
BUG=chrome-os-partner:31527
TEST=None
BRANCH=ToT
Change-Id: Ie6138075bd901225b4fee48fc4ab4fa2add24b45
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215131
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There was a way to brick the PMIC by programming its registers with a bad
configuration, this could prevent the AP from powering up properly (thus not
being able to unbrick it). The PMIC retains register state through S5 (presumably
due to RTC business) and they do not get reset at bootup unless the OTP reset is
asserted.
The OTP reset actually has to be asserted in a special(rather long as well)
sequence.
A bug was discovered while making this change(crosbug.com/p/31635): usleep does
not work for long delays. Since I needed at least 300ms on one of the delays I
used a workaround with a loop.
I also cleaned up some old tegra stuff and renamed things to be more semantic.
BUG=None
BRANCH=None
TEST=From the AP set a PMIC register from the default value of 0x7d to 0xfd:
user@ap~$ modprobe i2c-dev
user@ap~$ i2cget -f -y 0 0x1b 0x24
Check what the default state is, mine was 0x7d
user@ap~$ i2cset -f -y 0 0x1b 0x24 0xfd #or change 0xfd to something!=default
Cold reboot the dut("apreset" or "power on\npower off" will work) then check if
the PMIC registers got reset:
user@ap~$ modprobe i2c-dev
user@ap~$ i2cget -f -y 0 0x1b 0x24
0x7d(or whatever your default state was) #good
0xfd #bad, did not reset properly
Using "user@ap~$ i2cset -f -y 0 0x1b 0x24 0x00" instead will prove the bricking
of the PMIC/AP.
Change-Id: Iad96781ffde085befe6dea20edd255ca3e7e1357
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214360
Reviewed-by: Doug Anderson <dianders@chromium.org>
Change lid accel rotation matrix to orient lid accel to the base
accel.
BUG=none
BRANCH=none
TEST=Load onto samus, use accelread 0 and accelread 1 to make
sure lid and base accels match at a variety of locations.
Change-Id: I7a27f8e702c6c26ed671325183a87b52e5b3d06a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215944
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
This makes sure that we initialize all accelerometers when we leave
G3 because some accelerometers are not powered in G3.
Also, changed some of the print statements in motion_sense.c to
help in debugging.
BUG=none
BRANCH=none
TEST=tested on samus. verified if you go back and forth between
G3 and S0 that the lid accelerometer is always initialized by
using accelread command to verify that data is being updated.
Change-Id: I73effda4e6b04a629851e6c310d53b044c4aad42
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215943
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
When we do sysjump, the chipset might be in any of S0/S3/S5 states, and
thus we cannot just initialize the dual role state to its default state.
Instead, let's look at the chipset state and set the appropriate dual
role state.
BUG=chrome-os-partner:31724
TEST=On Ryu, do a sysjump and check dual role state.
BRANCH=factory-ryu-6212.B
Change-Id: I67abcc7fb1357d11498973a831ab8b32dad670ce
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215866
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Original implemenation of polarity only addressed Rd. This CL hopes
to address the addition of the Ra pull-down for powered accessories.
Truth table based on type-C specfication document is included in
source as well.
BRANCH=none
BUG=chrome-os-partner:28585
TEST=manual,
Setup:
<insert hoho into samus type-C port>
# from PD MCU console
typec <port>
Result:
See appropriate polarity. For example,
typec 1
Port C1: CC1 445 mV CC2 115 mV (polarity:CC1)
Superspeed USB1
<flip type-C accessory (hoho)>
typec 1
Port C1: CC1 119 mV CC2 426 mV (polarity:CC2)
Superspeed USB1
Also see correct polarity when just Rd is present.
Change-Id: I09073d731e4a6050281add3673cb4ec24c053da9
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215666
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
*** This breaks Plankton V1 support ***
This CL updates GPIO and PD configuration.
BUG=chrome-os-partner:31633
TEST=Build successfully. No board to test.
BRANCH=None
Change-Id: I9bbcde8aed15aa488e659a69dc87978532f33f13
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214823
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This command was intended to be used for testing, but we have moved on
to the compiled unit tests. Let's put this command behind a config flag
to save precious flash space. This frees up about 640 bytes.
To make sure no one is using this, I searched for "hostcmd" in
platform/ec/test and third_party/autotest/files/server/site_tests.
BUG=None
TEST=make buildall
BRANCH=None
Change-Id: I3192214b71c033c2388f687ed891203d1d119bb9
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214828
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Define SCL and SDA for I2C port 0 so that it is automatically unwedged
when it detects the bus has been wedged. Note, we can currently only
use this on one I2C port.
BUG=chrome-os-partner:31581
BRANCH=samus
TEST=load onto samus p2b that is having i2c port 0 problems and
wait for the bus to wedge, then verify it automatically unwedges:
[868.755442 I2C0 Addr:16 bad status 0x41, SCL=1, SDA=0]
[868.756013 I2C unwedge called with SDA held low]
Change-Id: I0ffb6a725af97155f734e2570574144ba4044f22
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215396
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Current ectool uses max outsize / insize from protocol v2
even if we have a v3 protocol ec. This makes some command
not working when actual size supported by ec is less than
max size from protocol v2.
This CL uses protoinfo command to read max size from ec
during the initialization process to correctly set max size
for ec with protocol v3+. For ec with protocol v2, protoinfo
command won't exist, hence ectool won't modify the max size
and used the size that we set when init the protocol.
BRANCH=none
BUG=chrome-os-partner:31660
TEST=Run 'ectool flashread 0 0x1000 /tmp/fr' in ryu
Change-Id: I226b6c2fb2f7e9be73032f2c5146d2710939b293
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214838
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Hibernate is not supported on STM32F0. Disable system hibernate so that
the system doesn't auto-reboot after an hour in G3. This also benefits
us in terms of firmware size.
BUG=chrome-os-partner:31665
TEST=Boot on Ryu. Check 'hibdelay' and 'hibernate' commands are absent.
TEST=Boot Ryu from G3.
TEST=Change default hibernation delay to 1 second. Put system in G3.
Check it does not reboot.
BRANCH=None
Change-Id: Ia01d2d74bc5c22c01e29e5877bd4bd38ee7dddc8
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214834
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=manual
BUG=chrome-os-partner:28585
TEST=manual,
Plug USB 3.0 capable device in both ports and both polarites on samus
and see device enumerate as superspeed. For example,
usb 2-3: new SuperSpeed USB device number 6 using xhci_hcd
In order you must first connected device (hoho) prior to configuring
mux via 'ectool --dev=1 --interface=lpc usbpd <port> dp'
Change-Id: Ia6b8a714ce9ae1539769399e51ff245d00202171
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214579
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Change the zinger software version returned by VDO_CMD_READ_INFO
to report the commit count portion of the version string to make
the software version automatically change. This software version
is important for debugging and is printed to PD console every time
a zinger is attached.
BUG=none
BRANCH=none
TEST=load onto zinger and samus, plug in zinger and see:
Dev:1 SW:2147 RW:0
compare to the version string in zinger binary and we see:
zinger_v1.1.2147-...
Change-Id: Ieafe89b4b16cee076be17bcbc6774bbd7fc24f8e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214428
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
PD_STATUS_HOST_EVENT is a non-zero bitmask, so use '&' to check the
proper bit(s) in the condition.
BUG=chrome-os-partner:31361
TEST=Manual on Samus. Plug + unplug zinger, verify that host events are
not set. Also, verify that 'pdevent' console command still sets the host
event.
BRANCH=None.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I15c61c3c872ce8e7425678b2c669fcfa1eec89a6
Reviewed-on: https://chromium-review.googlesource.com/214631
Reviewed-by: Alec Berg <alecaberg@chromium.org>
As we add more PD states, it's easy to forget to update the names of PD
states. This doesn't break any PD functionality so would be hard to
discover. However, it can easily confuse us when we are debugging. Add
a compile-time assertion to make sure it's updated.
BUG=None
TEST=Remove one names and check build fails.
BRANCH=None
Change-Id: I8b503e361b3418835cdf510dd39481eb7d998035
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212885
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If a ping is dropped, instead of cutting power immediately, we should
first try soft reset. If the soft reset packet is not received or an
ACCEPT packet is not seen in time, we'll then perform hard reset.
BUG=chrome-os-partner:31296
TEST=Add a console command to drop pings on Samus. Check that when a
ping is dropped, the power is not cut and the connection is
re-established.
BRANCH=None
Change-Id: Ifbee4124d55a9a7857a019ca823698f32911f3c7
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212925
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
After sending a soft reset, the port partner is supposed to respond with
an ACCEPT. If ACCEPT is not seen within PD_T_SENDER_RESPONSE, we should
try a hard reset.
This CL also changes the definition of SOFT_RESET state from an
artificial delay state to a state waiting for ACCEPT. With this, we are
now just waiting in DISCOVERY state after a reset and therefore we can
remove the 30ms artificial delay.
BUG=chrome-os-partner:31296
TEST=Along with the next CL to send soft reset on dropped ping, check
power doesn't drop when a ping is dropped.
TEST=Modify Samus to not send ACCEPT when a SOFT_RESET packet is
received. Check that we received HARD_RESET after SOFT_RESET.
BRANCH=None
Change-Id: Iddce33befa0c3c43228e68aac8e481d3da52db2a
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212924
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Every time a type-C source is plugged in, send a special VDM to
read device info. Device info will contain RW Hash (sha1), a
unique hardware descriptor (USB_PD_HARDWARE_DEVICE_ID), a
software version number just for debugging (USB_PD_DBG_SW_VERSION),
and a flag for if the device is in RW. This feature is off by
default and can be turned on by defining
CONFIG_USB_PD_READ_INFO_ON_CONNECT, currently defined for samus
and ryu only.
Renamed the read RW_HASH VDM to READ_INFO since it now returns
more than just the hash.
When device info is received, we store the RW hash. In the future
we will use this to check if device needs an update.
BUG=chrome-os-partner:31361
BRANCH=none
TEST=load onto a samus and a zinger. test when you attach zinger
we send a VDM, and we get device info printed to console. also
use "pd 0 hash" to query last hash received.
Change-Id: I0ca57651cf8506ea738b080a6cf8e7b020ef8724
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213832
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Add host event for PD up to AP. The PD toggles a gpio line to
EC causing an interrupt on EC. The EC then sends host command
down to PD MCU to get its status. There is a new status bit for
PD host event, so when EC see's the PD host event status bit,
it sends a PD host event to the AP.
There is currently only one host event for PD to AP.
BUG=chrome-os-partner:31361
BRANCH=none
TEST=added PD console command pdevent, which initiates the host
event. when sent, verified on EC that it sets the correct host
event bit using hostevent console command
Change-Id: If1a59a3232e2f9a49f272c6dee5319254d87b9a9
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213371
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds a new host commmand for sending RW updates to PD devices.
The host command has a variety of sub-commands for performing the
update, including: erase RW, reboot, write new hash, write flash.
To program zinger RW, you should send host commands in this order:
write new hash to all 0's
reboot (zinger boots into RO since RW hash doesn't match)
erase RW
write flash
write new hash to match contents of RW
reboot
This also adds an ectool command to write a new RW. Just pass it
the RW .flat or .bin file.
BUG=chrome-os-partner:31361
BRANCH=none
TEST=ectool --dev=1 --interface=lpc flashpd 0 0 zinger.RW.flat
Change-Id: Ia81615001b83ad7ee69b1af2bf1d7059177cde04
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213239
Reviewed-by: Randall Spangler <rspangler@chromium.org>
As a short term workaround for the I2C problem of PI3USB9281, we're
gating its SCL input when it's not addressed. This workaround will be
removed once we have the silicon fix.
BUG=chrome-os-partner:31526
TEST=Sanity check on P0 boards.
BRANCH=None
Change-Id: I57daf25f2ad2d94ac7e4192050b4d6bbdae9d51d
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214064
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The servo and the EC both output on the WARM_RESET line. Servo is open drain but
the EC was not. This caused a short whenever the servo tried to assert the
reset. The button still worked because the button is a lot stronger at pulling
down than the servo gpio.
Changing the WARM_RESET EC pin to open drain is an easy fix to this problem
without changing the hardware.
BRANCH=None
BUG=None
TEST=Warm reset via servo command should work. Warm reset button on servo always worked.
Change-Id: Ib615bc438a5726e40b0b502a197a57dbea6ee780
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213666
Reviewed-by: Dexter Yeh <dyeh@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Changed accelerometer orientation data to calculate correct
lid angle.
BUG=chrome-os-partner:27313
BRANCH=none
TEST=used "lidangle on" from ec console to print lid angle
and verified correct lid angle as I opened and closed lid.
Change-Id: If5f26ebe1b81449fe09741894a342a4a29e177e3
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214101
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
