We have hard timing requirements once we begin to output our host
command response, and most of the time is spent copying our response to
OBUF. Optimize our copy loops to remove needless increments and to avoid
needless struct dereference.
BUG=chrome-os-partner:61304
BRANCH=gru
TEST=Manual on kevin, verify the following performance metrics:
Time spent in shi_fill_out_status(): Was 40us, now 28us
Time spent in shi_write_half_obuf(): Was 60us, now 31us
Time spent in shi_write_first_pkg_outbuf:
Was 90us, now 37us (bad case)
Was 26us, now 16us (better case / less data copied)
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I04075c92744eeefe8f2be009e6598718c45143c4
Reviewed-on: https://chromium-review.googlesource.com/425330
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
It is not proper to use SET_BIT macro to clear a "write 1 to clear" bit
in a register. It will also clear other bits if they are also set.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; boot up on gru, run ectool stress test for a while
without problem.
Change-Id: I0c5a850e85e41820515b1a8f15bb43d77397737f
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/425589
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Setting HICTRL.FW_OBF clears the HIKMST.OBF and STATUS.OBF flags but it
does not deassert IRQ1 when already asserted. To make sure IRQ1 will
also be deasserted need to emulate a host read.
Modified drivers:
1. lpc.c: emulate a host read to clear OBF and deasserted IRQ1.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; Run FAFT items related to Power on/off, reboot,
and keyboard on Wheatley.
Change-Id: Ibf0ff3b8a4eeece853916e4e19d67fcc7ae2e989
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/419909
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since ec doesn't support old-style host command, this CL removes
unsupported parts in npcx's lpc driver and lets the hand-shaking
mechanism between host and ec as easy as possible. It makes sure only
following conditions that ec can clear processing bit of host command.
1. Received LRESET signal.
2. In lpc_init() initialization function caused by sysjump.
3. If command is valid, it will be cleared in lpc_send_response_packet()
called by host command task.
4. If command is invalid, it will be cleared in lpc_send_response()
after the response package is ready.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=wheatley; do stress test on wheatley.
Change-Id: I53d17fd9e09b7fb080e4bf71437392bf43db6258
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/422707
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The EC on Eve has VCC1_RST connected to 3.3DSW which drops when
resetting for recovery.
Since I need this to work on current boards treat Eve the same as
Wheatley and use the workaround that always reports reset-pin
instead of power-on status.
BUG=chrome-os-partner:61028
BRANCH=none
TEST=successfully enter recovery mode on eve with the keyboard
Change-Id: Ica583d9a95d78689ee1b21ccfa882fced2a414d9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421128
Reviewed-by: Shawn N <shawnn@chromium.org>
GCC 5.3 and 6.2 complain about the the i2c_irqs array being defined as
static because it's used by a non-static inline function.
Since i2c_handle_sda_irq is only used in the i2c.c file, it makes sense
to make it static.
Additionally, remove the inline keyword for i2c_handle_sda_irq since
it's a huge function, if it were used more than once, we wouldn't want
it to be inlined.
chip/npcx/i2c.c:462:22: error: 'i2c_irqs' is static but used in inline
function 'i2c_handle_sda_irq' which is not static [-Werror]
task_disable_irq(i2c_irqs[controller]);
npcx_evb/RW/ec.RW and npcx_evb_arm/RW/ec.RW.flat each shrank by 20 bytes.
npcx_evb/RO/ec.RO and npcx_evb_arm/RO/ec.RO.flat each shrank by 64 bytes
BUG=none
BRANCH=none
TEST=make buildall passes under GCC 4.9.2, 5.3 and 6.2
Change-Id: I79691bb57083fd925f9c4be06de706f676a1d043
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/403502
Reviewed-by: Shawn N <shawnn@chromium.org>
There's a small period between ec cleared EC_LPC_CMDR_BUSY status bit
for sysjump and executed notify hook function to let lpc driver disable
lpc's interrupts. If ec received a new host command in this period,
EC_LPC_CMDR_BUSY status bit has chance not to be cleared since ec
already jumped to the the other region. In case ec and host enter
dead-lock loop, we need to clear it on lpc_init().
Since HIPMnST only can be reset by core domain reset, it's better to
clear EC_LPC_CMDR_BUSY status bit when LRESET asserted. It makes host
can reset host command mechanism if something wrong.
BRANCH=none
BUG=chrome-os-partner:60928
TEST=make BOARD=reef; pass the tests mentioned in issue #60928
Change-Id: I08ac0515cb2cfee277a7c7704d131574d928fb6b
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/419908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The original thought of setting LRESET_PLTRST_MODE to 1 is to remove the
need to reinitialize host module registers whenever LRESET# occurs in
order to save time when boot-up.
However, some of these registers will be reset by core domain reset. It
means every time LRESET is de-asserted, we need to initialize the host
setting again. Therefore, setting LRESET_PLTRST_MODE to 1 is unnecessary
and sometimes dangerous. If BIOS believes LRESET will reset ec's host
state machine to default but ec not, it will cause unexpected behavior.
Modified drivers:
1. lpc.c: allow LRESET/PLTRST generate host domain reset
BUG=chrome-os-partner:60211
BRANCH:none
TEST=make buildall. run "dut-control pwr_button:press; sleep 11; dut-control
pwr_button:release; sleep 7; dut-control pwr_button:press; sleep 1;
dut-control pwr_button:release". Verify keyboard works normally.
Change-Id: I94d428cde69f828468547c44844983f25686ea04
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/417745
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
__hw_clock_event_set() is not reentrant and may be called from both our
event timer ISR and our hwtimer ISR when hwtimer is close to wrapping.
Modify the interrupt priority of our hwtimer int to match our event
timer int so that one cannot preempt the other. Originally the priority
was changed to allow the hwtimer ISR to run first in case both are
pending, but this condition can be handled cleanly and isn't a big
concern.
BUG=chrome-os-partner:60470
BRANCH=gru
TEST=Pass 500 S/R cycles on kevin with hwtimer wrap rate sped up 300x
(roughly equivalent to 150,000 real S/R cycles).
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ied466f14661f04c8662b5db709c0e3770a5bb200
Reviewed-on: https://chromium-review.googlesource.com/417060
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit ac28ec53b63a02c4d25e8a222d13595bc857fef0)
Reviewed-on: https://chromium-review.googlesource.com/417112
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
gru has circuitrythat selects the charge LED color based on the
frequency of the PWM.
By adjusting the PWM frequency instead of just the duty, we gain more
control over the brightness of the charge LED.
BUG=chrome-os-partner:54155
BRANCH=gru
TEST=activate each LED in turn and confirm color and brightness
Change-Id: Ie653125a528595c1ec68aea4d02cb70595a1b151
Signed-off-by: David Schneider <dnschneid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/415517
Reviewed-by: Shawn N <shawnn@chromium.org>
Common code is more flexible and supports more parts, so delete the
npcx-only register translation code.
BUG=chrome-os-partner:60029
BRANCH=gru
TEST=Manual on gru, run 'flashrom -p ec --wp-enable' and check that 0x28
gets written to SR1, which matches our desired 'protect botton 128KB',
according to the datasheet. Also run 'flashrom -p ec --erase' then read
back EC SPI contents, verify ROM is erased except for first 128KB
region.
Change-Id: I526401997ff7ec77f2a6047a4a9af74a671ed69a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413228
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 43634d36d273887b1f2349c333a7b4b229a83365)
Reviewed-on: https://chromium-review.googlesource.com/415498
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
If UMA is locked, read and write access to SR* regs will fail, and we'll
be unable to determine or change our write protect state. Save our SR
regs before enabling UMA lock, and bring down UMA lock for a brief
period when writing SR regs.
BUG=chrome-os-partner:60029
BRANCH=gru
TEST=Manual on kevin with SW sync enabled.
flashrom -p ec --wp-enable -> verify success, check flags:
Flags: wp_gpio_asserted ro_at_boot ro_now
Reboot host, check flags:
Flags: wp_gpio_asserted ro_at_boot ro_now all_now
Verify flashrom -p ec --wp-status shows protected, and flashrom -p ec
--wp-disable fails.
Also verify same state after EC reset.
Boot into recovery mode, check flags:
Flags: wp_gpio_asserted ro_at_boot ro_now
Remove WP screw, reboot EC, check flags:
Flags: ro_at_boot ro_now
Verify flashrom WP status shows protected, and flashrom WP disable
succeeds and clears all flags.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I17e32f7305600183e7fcb87f69a3feb88978f94e
Reviewed-on: https://chromium-review.googlesource.com/412977
(cherry picked from commit 6cfc0d0dd030b8b0334f99e99950a52fcf8267af)
Reviewed-on: https://chromium-review.googlesource.com/415497
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The mux for selecting source clock of ITIM will introduce a delay
and have a chance to make ITIM's source clock and core clock are
asynchronous. We need consecutive reading for ITCNT32 no matter source
clock is APB2 or 32k.
Modified sources:
1. hwtimer.c: Add consecutive reading for ITCNT32
BRANCH=none
BUG=chrome-os-partner:34346,chrome-os-partner:59240
TEST=No time stamp symptoms occur on wheatley for 30 hours.
Change-Id: I8b54e93b320e3ea74fc3d6ea13f0d178f9c449cd
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/412505
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The 'cycles' register will be clobbered by our macro, so it must be
specified as an output operand that may also be used as input.
BUG=chrome-os-partner:60000
BRANCH=gru,strago,glados
TEST=Build + burn wheatley, verify alignment exception is not
encountered on boot. Also verify produced assembly is still correct:
100a89a6: 2303 movs r3, #3
100a89a8: 3b01 subs r3, #1
100a89aa: d1fd bne.n 100a89a8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I1be03a006967aed6970dbac5d98a19a31e0b7d49
Reviewed-on: https://chromium-review.googlesource.com/412441
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear
the wake masks when the SMI is invoked. For S0ix, EC sets and clears
the wake mask via this patch.
These functions are directly invoked from the state machine transition
states. During S0ix entry, the wake mask for lid open is enabled.
During S0ix exit, the wake mask for lid open is cleared. All pending
events are also cleared.
BRANCH=none
BUG=chrome-os-partner:58740
TEST=test lidopen in S0ix
Change-Id: I398fdba2b9bba1f6caef46f8dc71c7de3b669d08
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/401070
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
If our 32-bit usec timer is close to overflow, we may deep sleep several
times in succession without making any adjustment to our count, causing
deadlines on the other side (eg. HOOK_TICK expiration) to be reached much
slower than expected. Avoid this by not entering deep sleep if our timer
is about to overflow. This will result in a <= HOOK_TICK_INTERVAL (200ms
interval) period of not entering deep sleep, every ~4300 seconds.
BUG=chrome-os-partner:59240
BRANCH=gru
TEST=Verify 3x kevin units survive 16 hours in S3 without EC watchdog.
Change-Id: I2126458be8820f78212e19c2bb79242ff1194f6f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409673
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
- Wait for ITEN bit to be set / cleared, since writing this bit just
sets a 'request'.
- Ensure ITIM_EVENT_NO reg is set with minimum value 1, per the
datasheet.
- Don't dsleep if our wake event is in the past (eg. wake event will
occur any time now)
BUG=chrome-os-partner:59240
BRANCH=gru
TEST=Manual on kevin, verify that dsleep period never exceeds expected
wait period. Also verify that EC watchdog doesn't occur after 5 hours in
S3.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iedb2723c3f12b74dea66082b1d8b8ce1b6e7d945
Reviewed-on: https://chromium-review.googlesource.com/409672
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When GPIOC6/GPIO76 are not selected as SMI/SCI function(ie. selected
as GPIO), the reading of SMIB/SCIB will be a fixed value. This means
it cannot reflect the actul SMI/SCI status. As a reault, use SET_BIT/
CLEAR_BIT macro to toggle SMIB/SCIB is not feasible. Firmware should
read the SMI/SCI status from VWEVSM(2) register before setting it.
This CL defines some macros to achieve it.
In the previous CL, SMI/SCI negative polarity is conditionally
disabled. However, the negative polarity is not used in current
firmware design. Set the SMI/SCI polarity as postive unconditionly by
default.
Modified drivers:
1. lpc.c: use macro NPCX_VW_SMI/NPCX_VW_SCI to generate Virtual wire.
use SMI/SCI postive polarity uncontionally by default.
2. register.h : define macro to handle SMI/SCI virtual wire.
BUG=chrome-os-partner:34346
BRANCH=none
TEST=make buildall; try hostevent on Wheatley and check virtual wire
signal is correct on logical analyzer.
Change-Id: Id4a7748addeaa3b35f280ff29f6fcd8a08b9894b
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/400161
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Prior x86 boards have had GPIO for toggling RCIN directly on the PCH,
although many likely had HW-assisted methods as well.
With eve we need to generate an eSPI Virtual Wire for RCIN, but in reality
software control over RCIN Virtual Wire is not available with the npcx EC,
so the legacy LPC interface for pulsing KBRST must be used instead as this
is the only way to generate RCIN.
This method will likely vary on different EC chips, but for skylake it
can just be abstracted into the LPC module.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=successful 'apreset warm' on eve EC console
Change-Id: I7f9e7544a72877f75d05593b5e41f2f09a50e1c9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400037
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable the chipset_reset_hook by adding interrupt trigger on
pltrst assertion and fix the compilation when built with
CONFIG_CHIPSET_RESET_HOOK enabled.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=build with CONFIG_ESPI and CONFIG_CHIPSET_RESET_HOOK
Change-Id: I64eb7a1acc58c07beba0d28f94d95ef33d7220fb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400035
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The check for whether or not to send an SMI needs to check the
same status bit that it is using to indicate that it is going
to send an SMI. The SMIE bit is enabled in lpc_init() so it is
always set.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=shutdown with lid close event at developer screen
Change-Id: I9a0f34025c4fa11175fca7be34224ec680bffbef
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400033
Reviewed-by: Shawn N <shawnn@chromium.org>
The host command parameter and response buffers should be explicitly
aligned by the LPC/SPI/I2C drivers. But the host command handlers don't
know that, and the structs are all __packed, so the compiler generates
horribly inefficient ARM Cortex-M code to cope with unaligned accesses.
Add __ec_align{1,2,4} to force the param / response structs to be
aligned. Use it in a few structs now which were straightforward to
test. It should be added to more structs as space is needed, but that
would make this change unwieldy to review and test.
Add CONFIG_HOSTCMD_ALIGNED to enable the additional alignment.
Currently, this is enabled only for LM4 and samus_pd, so that EC code
can be tested without affecting other non-samus ToT development (none of
which uses LM4).
Fix the two handlers that weren't actually aligned (despite one of
them having comments to the contrary).
Also, add a CHROMIUM_EC define that can be used to determine if a file
is being compiled for an EC target. We need that so that we only force
structure alignment for EC binaries. On the AP side, buffers may not be
aligned, so we should not force alignment.
BUG=chromium:647727
BRANCH=none
TEST=Flash samus and samus_pd. Boot samus and run a bunch of ectool
commands (with and without --dev=1, so it tests both EC and PD).
System boots and all commands return expected results.
Change-Id: I4537d61a75cf087647e24281288392eb85f22eba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/387126
In current FW implement, there are two ways to generate SMI/SCI:
(1) Controlled by GPIO module register.(#define CONFIG_SCI_GPIO)
(2) Controlled by PM module register.(#undef CONFIG_SCI_GPIO)
This CL fix for case(2):
In this case, these two dedicated pins(GPIOC6/GPIO76) are used
as SMI/SCI and must be enabled by pinmux. Set the related pinmux
at initial.
By default, the SMI/SCI polarity is negative. This means SMI/SCI
is inverted when writing to SMI/SCIB but not inverted when reading
from them(see Section 5.2.2, figure 61 in datasheet). It will cause
the code more complicated to implement. Disable negative polarity
at init.
Modified drivers:
1. lpc.c: set pinmux for dedicated SMI/SCI pins and disable the
negative polarity.
BUG=chrome-os-partner:34346
BRANCH=none
TEST=make buildall; try hostevent(lid switch) on Wheatley with
CONFIG_SCL_GPIO undefined.
Change-Id: Ia317e54deb6861d7189b3594bd7414b53408b933
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/396718
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Enable valid bits of SCI#/SMI# of eSPI's VW if there's no CONFIG_SCI_GPIO
definition in board-level driver. This CL also fixed the order of VW
event bits in comments.
Modified sources:
1. espi.c: Enable valid bits of SCI#/SMI#.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make all; test nuvoton IC specific drivers
Change-Id: I8d094513284b4ed42c5c26fe1975d71bbf050aa4
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/396618
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reset-on-hibernate wake performs a soft-reset, which re-initializes GPIO
states to ROM POR values. Therefore, it is necessary to re-init GPIO
states once again based on board-level GPIO settings.
BUG=chrome-os-partner:58077
BRANCH=gru
TEST=Run `hibernate` on gru, wake, then run `bd99955_dump`. Verify
actual register values are printed rather than zeros.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib3eb1dd6aa264d00d42d8e386bfd1ef7f6cf7717
Reviewed-on: https://chromium-review.googlesource.com/395426
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
spi_transaction() can be called from motionsense, hooks, hostcmd,
console, and chipset tasks, so add a mutex to ensure an in-process
transaction isn't preempted by another transaction.
BUG=chrome-os-partner:57912
BRANCH=gru
TEST=On kevin, run "while true; do ectool motionsense odr 0 0; sleep 1;
ectool motionsense odr 0 1000000; sleep 1; done", verify watchdog crash
not encountered after 20 minutes.
Change-Id: I7ec495bab295dc03ce02372c20e5c7c5c196715d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391892
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit eabdea443775fab834aaabbb7afae871306c7530)
Reviewed-on: https://chromium-review.googlesource.com/392226
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The application may need to read/write/erase the flash memory,
but we not want console users to do so. This CL adds
CONFIG_FLASH_PHYSICAL, which allows the higher-level CONFIG_FLASH
to be undefined while still providing the chip-specific
flash_physical_* accessor functions.
There aren't many board.h files that needed changes, since
CONFIG_FLASH_PHYSICAL is enabled by default, just like CONFIG_FLASH.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
See that it still boots, updates, wipes, restores, etc. without
linking common/flash.o in the production image; and that the
flash commands are still there in the dev build.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I7eb1bbcb414b1c70ee427c4fcb5cea899dbb9e93
Reviewed-on: https://chromium-review.googlesource.com/391188
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The pwm prescaler wasn't being calculated properly when used with
the 32 Khz clock.
BUG=chrome-os-partner:57526
BRANCH=none
TEST=Manuel
- With PWM frequency set to 100Hz, I verified on the scope that
the duty cycle changed from 0 to 100% in 10% increments.
- Verified on the scope that PWM frequency could be set to 100Hz,
200Hz, 300Hz, 400Hz, and 2600Hz.
Change-Id: Idf8ffb6b20d469c9ea58e5a34e944f79d475eb15
Reviewed-on: https://chromium-review.googlesource.com/388814
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
NPCX reboots by triggering the watchdog which in turn causes
the watchdog reset flag to be set as one of the system-wide
reset_flags. However, other software can confuse the presence
of the watchdog reset flag as a panic.
This patch selectively sets the watchdog reset flag only if we're
not explicitly doing a soft or hard reset or waking from hibernate.
Patch created by Mulin Chao <mlchao@nuvoton.com>
BUG=chrome-os-partner:56594
BRANCH=none
TEST=panic reset no longer observed
Change-Id: I016b59ffda4f6334cf41e196960edcbb87f6c049
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388853
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
This commit adds a function that allows the real-time clock to be
printed on the EC console. This could be helpful in trying to correlate
events between the EC's log and the kernel's.
BUG=chrome-os-partner:57731
BRANCH=gru
TEST=make -j buildall
Change-Id: I5e20692a173bddea3dc5c20cc0f2061cc170ce7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/388856
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously, there was no way to identify which flash chip was used by
the EC, for ECs using an external SPI flash. Now, 'ectool flashinfo'
will print more information about the SPI flash chip in these cases.
BUG=chrome-os-partner:56765
BRANCH=any EC with MEC1322 or NPCX still going through factory
TEST=define CONFIG_HOSTCMD_FLASH_SPI_INFO, then
'ectool flashspiinfo' on samus indicates no SPI flash info,
and prints additional info on chell and kevin. Without
the config defined, all platforms report no spi flash info.
CQ-DEPEND=CL:386368
Change-Id: I3c162f7ad12ed4b30ab951c03f24476683382114
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385702
Reviewed-by: Shawn N <shawnn@chromium.org>
Before performing a sysjump, ensure that:
1. LPC interrupts are disabled : Ensures interrupts are not taken until
next enable.
2. LPC window is closed by writing 0xfffffff8 to window base addresses:
Prevents any memory corruption by host.
BUG=chrome-os-partner:57642
BRANCH=None
TEST=Verfied that LPC communication works after sysjump to RW.
Change-Id: I7b7826b2544f1c94cfa9c96b6ac82bc3517b1820
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388755
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
1. interrupt enabling should be the last thing done when lpc_init
completes required intialization
2. memset to 0 of static uninitialized variables is not required. Remove
that.
BUG=chrome-os-partner:57642
BRANCH=None
TEST=Verified that LPC communication is fine after sysjump to RW.
Change-Id: Ib8891dccf2b301590ebca41b75680d954d88a4d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388752
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
We should clear STASTR to release SCL only after NACK/STOP bits are set.
If an interrupt which priority is higher than i2c's issues at this moment,
i2c hardware might not generate NACK since SCL is already released by
clearing stall's pending bit.
Modified sources:
1. i2c.c: Fixed bug i2c sometime cannot generate NACK during Read Byte.
BRANCH=none
BUG=chrome-os-partner:34346,chrome-os-partner:57452
TEST=make buildall; passed "while(1); do; ectool i2cread 8 0 0x50 0x44;
done;" on reef.
Change-Id: I68ee5bf3d703cbe4fceefcfcc9afab9cb14bc2dc
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/386586
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable the SHI interrupt only after we have received and begun
processing our host command. Disable the SHI interrupt once our
transaction is complete (with either success or error status). This will
prevent the SHI interrupt from being asserted at the same time as the CS
interrupt, which can lead to the SHI interrupt being serviced first.
Also, it avoids needless, non-useful SHI interrupts during error
transactions.
BUG=chrome-os-partner:55710,chrome-os-partner:55795,chrome-os-partner:56254
BRANCH=None
TEST=Manual on gru. Stress test flashrom w/ unpowered Donette attached
(for host command spam), verify no errors encountered after 100 minutes.
Also verify host command interface functions properly after sysjump.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/384583
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 668763721aab31a102ead348d7cfe1c72f50cb71)
Change-Id: I7292d1b34d3e1c71628a8b5d663ce9fd865493f4
Reviewed-on: https://chromium-review.googlesource.com/386447
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
We found the api utility in ROM doesn't enable burst mode of GDMA. It
influences the performance of FW download a lot. The CL modified GDMA
for moving the code of the other region from flash to ram. And move a
function that kicks off GMDA transactions to suspend ram in case this
utility is erased by itself. This issue will be fixed in our next
generation.
Modified sources:
1. system.c: Implement GDMA bypass.
2. system_chip.h: Import flash addresses for GDMA bypass code.
3. registers.h: Add GDMA register definitions.
4. cortex-m/ec.lds.S: Add lowpower_ram2 section in linker script.
BRANCH=none
BUG=chrome-os-partner:56794
TEST=make BOARD=npcx_evb; test sysjump and measure download time
Change-Id: I8490f8f2e5a8cdcb6fd10511878c4a4af8073bbf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/381779
Commit-Ready: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
TTC must be written twice, otherwise the value will be lost on EC reset,
even if VBAT stays stable.
BUG=chrome-os-partner:57010
BRANCH=None
TEST=On kevin, run 'rtc set 55555' then trigger cold reset through
servo. Run 'rtc' on subsequent boot and verify timing ticks did not
reset to zero.
Change-Id: If05b698e75eece5f8879a109b98886b547eb71a4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382654
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The CTR was set to 1 less than the max PWM value, so when the DCR
is set to max PWM value, duty goes to zero. The bug is fixed by
setting CTR to PWM max vlaue.
BUG=chrome-os-partner:57052
BRANCH=None
TEST=Manual on terminal.
> pwmduty 1 raw 0
Setting channel 1 to raw 0
1: disabled
> pwmduty 1 raw 65535
Setting channel 1 to raw 65535
verified that screen didn't blank
Change-Id: I10885d382f1bd252a5e7355da99dc00bd876e29f
Reviewed-on: https://chromium-review.googlesource.com/381632
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to improve the performance of sysjump, the CL increases the clock
freq of ec to 50M HZ (The maximum freq rate for SPI flash.). Once ec jumps
into the other region successfully, the clock freq is restored to the
default value (15MHz) in main routine.
Modified sources:
1. clock.c: Add clock_turbo for speed up clock's freq to max.
2. clock_chip.h: The declarartion for clock_turbo.
3. system.c: Speed up clock rate before downloading FW.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=npcx_evb; test nuvoton IC specific drivers
Change-Id: I996e35fff336e6292599497feb1ee6c2f95becba
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/381799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
