This change enables configs for:
CONFIG_USB_SERIALNO: a programmable serial number for servo_v4
CONFIG_CMD_GPIO_EXTENDED: ability to change GPIO functions on the command line.
BUG=chromium:571476
BRANCH=None
TEST=serialno set abcdef; serialno load; reboot; gpioget/gpioset
Change-Id: I0e871d256e41022d3bb9985e590864a6c4cdf6a4
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348391
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This change is motivated by an internal use case.
BRANCH=none
BUG=none
TEST=make buildall -j
Successfully used the exported functions on Cr50.
Change-Id: I5a54b4ea407866c7d7a4bd075d7773ac81e00930
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348215
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Initialize the charge suppliers after change manager is initialized,
otherwise charge supplier current & voltage values will be overwritten
to -1 by the charge manager ini function.
BUG=chrome-os-partner:53788
BRANCH=None
TEST=Observed there are no "CL: p(port) s(supplier) i-1 v-1" prints
on the EC console.
Change-Id: Id0212c502d5833c016ac79ee15d21304d6d7ceb2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347896
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This moves PP5000 and PP3300 enable early into board_init() and
increases priority of board_init() so that it runs before any TCPC
or PD init hooks which communicate with the TCPCs via I2C.
This hack also makes it so we don't shut off PP3300 for the time
being, at least until we get the proper sequence down and can avoid
I2C errors.
This probably is not the permanent solution, but for now it prevents
a lot of I2C errors from occurring.
BUG=chrome-os-partner:53549
BRANCH=none
TEST=booted on reef, no longer see I2C wedge error messages
Change-Id: I87e2e99aa3e1152cd10a2bfdd749d6e0dbd981a8
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346633
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Move power rail and pmic enable control to be handled at
board level due to specific board design.
Modify rsmrst where assertion is pass-through at all time
and de-assertion is only pass-through at power up.
BUG=chrome-os-partner:53666
BRANCH=none
TEST=amenia is able to handle apreset warm/cold, pmic shutdown,
soc reset/shutdown.
Change-Id: I7ff819d88d0e194073bee8f02b1e3fa70ca44ba7
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347370
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
This fixes two race conditions that lead to a watchdog timeout:
1) ticks_to_usecs()
common/timer.c:process_timers() wraps its body in a
"while (next.val <= get_time().val)" loop meant to ensure that
it never returns after having scheduled an expired timer
(to address potential __hw_clock_event_set() overflows/underflows).
However get_time() through __hw_clock_source_read() calls ticks_to_usecs()
which "expands" the hw_rollover_count by a truncated clock_div_factor which
causes that loop condition to observe a "current time" that is up to ~15us
in the past (assuming a 24MHz clock). This race arises frequently with
workloads that repeatedly sleep for a short duration.
2) __hw_clock_event_irq()
The HW timer rollover interrupt was configured to be higher priority than
the event timer interrupt (i.e. it can preempt it) which is problematic if:
- There is a scheduled deadline soon after a "clksrc_high / .le.hi" boundary
- An earlier (before the clksrc_high rollover) event timer interrupt kicks in
- After the event timer interrupt handler gets to "now = get_time()"
in common/timer.c:process_timers() the rollover interrupt triggers
incrementing clksrc_high (i.e. the overflow case)
- The rollover interrupt handler arms the event timer to trigger at
that deadline (mentioned in the first bullet) and returns
- The original event timer interrupt handler resumes execution but finds
no events to schedule since the "timer_deadline[tskid].le.hi == now.le.hi"
clause won't evaluate to true. It will then call __hw_clock_event_clear()
before returning causing a watchdog timeout
This commit also contains a fix to properly initialize the HW timer
after a sysjump.
BRANCH=none
BUG=none
TEST=Reproduced both races and successfully tested the fix. The workload I was
using to reproduce (typically within an hour) has been running smoothly
for the past 24 hours.
Change-Id: Ic0b0958e66e701b52481fcfe506745ca1c892dd1
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347465
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When the AP or EC is off, the RX line is low. Holding the UART RX line
low causes an interrupt storm. This change disables the UART TX and RX
on the peripheral when the device is powered off so the interrupts wont
be triggered.
BUG=chrome-os-partner:53514,b:28885578
BRANCH=none
TEST=run taskinfo on cr50 and make sure the IRQ count for 181 is a
reasonable number.
Change-Id: I42c779253860a2b1dd27ab41fb7097c887cc23ff
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347355
Use the power and servo connection states to enable and disable the
EC and AP UART output. Contention between the cr50 and servo
can prevent either uart from working, and possibly damage kevin or
servo. If both UARTs are enabled, then cr50 cant know if servo is
connected, so it is best if the UARTs are disabled before connecting
servo.
If servo is connected or if a device is not powered on then the UART
output wont be enabled. The two UARTs are enabled separately and one can
be enabled without the other. Any disabled UART will be monitored for a
servo connection. If servo is detected, then all UARTs will be disabled.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=manual
Power on the EC only. Check only the EC UART is enabled.
Without disabling the uarts power on the AP and verify both are
now enabled.
Turn of the AP. run 'uart enable. Verify only the EC UART is
enabled. Then attach servo and check that the AP and EC UART
are disabled.
Change-Id: Ife27c9360e91b07f86ff8bfcec7f4fd423c31d25
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342828
There are a couple of issues that cr50 has when it cannot know the state
of servo, the EC, and the AP. This change adds support so we can detect
when the AP or EC has been powered on and when servo has been connected.
It uses the UART RX signals to monitor the power state of the AP and EC.
The TX signals are used to monitor the state of servo.
BUG=chrome-os-partner:52056,chrome-os-partner:52322
BRANCH=none
TEST=verify device states are correct when the AP and EC are powered on
or off and when Servo is attached or detached
Change-Id: Id0a2281b65cb367ecc8d0ca2f9a576672318a5fb
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344019
Only way to set alarm previously was through
rtcalarm command on EC console. Implemented
interface through ectool so that the AP can set
it as well.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=from AP console, run ectool rtcalarm <sec>
Should see [event set 0x02000000] from EC
console in approximately <sec> seconds.
Change-Id: I3202b826cb994dbca456b8b9c22bbca4dbe2766a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347493
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Used #define CONFIG_FLASH_NVMEM to have functions in
/board/tpm2/NVMem.c utlitize on chip Nvmem functions.
On chip NV Memory availability is tied to an internal nvmem
error state which itself only depends on finding at least one
valid partition.
Added nvmem_is_different and nvmem_move functions which were
needed to complete the tpm2 platform interface. In addition,
added unit tests to support these two new functions.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass.
Tested with tcg_test utility to test reads/writes using the
command "build/test-tpm2/install/bin/compliance --ntpm
localhost:9883 --select CPCTPM_TC2_3_33_07_01".
Change-Id: I475fdd1331e28ede00f9b674c7bee1536fa9ea48
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346236
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Enabled CONFIG_FLASH_NVMEM and its associated configs. Added
user definitions along with buffer lengths. Added board
specific functions for sha computation and getting user
buffer lengths required by the NvMem module.
This CL does not include calls from cr50/board/tpm2/NVMem.c.
Those calls will be modified in a subsequent CL.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
The only call to any NvMem functions is nvmem_init().
Loaded code and verified via console that it boots
up properly. Also executed 'make runtests', but
that really only tests regression and not the new
board specific changes.
Change-Id: Iddc8d05703707247d26a8f22dca3ac9cc3c6ad1e
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345633
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Full implementation of NvMem read, write, and commit functions.
Includes partition definitions, shared memory allocation, and
initialization function.
Includes a set of unit tests located in ec/test/nvmem.c which
verify functionality.
This module is required by Cr50, however this CL does not
include any Cr50 specific code.
BUG=chrome-os-partner:44745
BRANCH=none
TEST=manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass
Change-Id: I515b094f2179dbcb75dd11ab5b14434caad37edd
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345632
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change provides a console command for setting,
and loading a usb serial number from flash. This
feature adds CONFIG_USB_SERIALNO, and currently only
has a useful implementation when PSTATE is present.
BUG=chromium:571477
TEST=serialno set abcdef; serialno load; reboot
BRANCH=none
Change-Id: I3b24cfa2d52d54118bc3fd54b276e3d95412d245
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337359
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The console adc command prints adc values in the
order they appear in hardware, however they are lableled
in the order they are enumerated in board.h, which is not
necessarily the same.
This prints the correct name and value pairs, and removes
the adc_read_all_channels function which is not otherwise
used.
BUG=chromium:571476
BRANCH=None
TEST="adc" command associates correct values with names now.
Change-Id: I688641953d20082224b4120eaefe0d634ad4c74c
Signed-off-by: Nick Sanders <nsanders@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340892
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The counter used for prime generation should be
incremented after each success / failure. Not doing
so results in duplicate primes being picked when
a label is explicitly specified.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: Ib2fd0e7fa6255b04946e6d2808e8c67a2199fb55
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/346056
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
BUG=chrome-os-partner:53729
BRANCH=None
TEST=Manual on gru. Verify .rodata.evtsrcs section is non-empty in
ec.RO.map. Verify that we're no longer spammed with HC 0x67 (due to
constantly asserted interrupt).
Change-Id: I57ad1ba7fbdd99dfab84341560aff094ce9bc5b6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347415
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The install script builds and installs the raiden module, it also copies
the udev rules file into /etc/udev/rules.d and updates the module alias
and dependency information.
The install script will also retrigger udev to process rules for all
devices that have the Google Vendor ID (0x18d1). This ensures that
any devices that are connected when the install is run will immediately
be available for use (as opposed to requiring that these devices be
unplugged and replugged before use).
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=Remove udev rules file
Remove raiden.ko module, aliases, and dependency information
Reboot workstation
Run ./install
Plug in CCD capable device
ls /dev/google
Change-Id: I7bcb02f05ee84738a6259800afc4d0c69bea9e69
Reviewed-on: https://chromium-review.googlesource.com/347092
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Third party code includes standard system headers,
but may not have include paths configured for the
platform.
Remove the dependency between assert.h and
platform headers util.h, and panic.h.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=make buildall succeeds
Change-Id: Ic8d4dc1944765d2f0f80782afa574d7b8e54eb0f
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/347080
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
ec_readmem_dev_v2() was copy/pasted from ec_readmem_dev(), but we forgot
to switch over the fallback 'fake_it' case to the new ioctl format. This
case is used over transports like SPI, which don't implement
cmd_readmem.
BUG=none
TEST=run `ectool version` on kevin (with cros-ec-spi) and don't see:
ioctl -1, errno 25 (Inappropriate ioctl for device), EC result 255 (<unknown>)
BRANCH=none
Change-Id: I4335f8fc3d43169cf628e26cadf1ac8d263955f2
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347111
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Stephen Barber <smbarber@chromium.org>
These must be initialized in order for charge_manager to select a port +
input current limit.
BUG=chrome-os-partner:53578
BRANCH=None
TEST=Attach 5V USB-C charger on Reef, verify "New chg" print is seen
along with "CL: p0 s1 i3000 v5000]" print.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia6139d9e9c6acd17ac587b32280f11927741672d
Reviewed-on: https://chromium-review.googlesource.com/347043
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This allows the AP to protect a I2C passthru bus. A board-specific
function then defines what I2C commands are allowed, so that we
can white/black list some addresses (e.g. I2C address allowing
PD chip FW updating).
BRANCH=none
BUG=chrome-os-partner:52431
TEST=Book elm-rev1
Change-Id: Ib106924418b16388ea8ea53c7b6bda6ef92e1d09
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/345761
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@google.com>
The gpio settings for the USB_PD_RST_ODL signal had the default
state high while the power enable, EN_USB_TCPC_PWR, was low. This
is combination of settings is invalid for the part. Therefore,
keep USB_PD_RST_ODL low until board_set_tcpc_power_mode() is called
to bring the pd chip online.
BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel confirmed things still working.
Change-Id: I8b6b54a474c00165a4d0af944fb60f2923b9ef5c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347000
Reviewed-by: Shawn N <shawnn@chromium.org>
The USB_C0_PD_INT signal is actually at 3.3V levels. Don't mark
the voltage sensitivity to 1.8V.
BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel ran with resulting image. Nothing bad observed.
Change-Id: I36bc3f911b715dc967cc8f23dfc70c3d0e5023d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346734
Reviewed-by: Shawn N <shawnn@chromium.org>
board_reset_pd_mcu() was provided to ensure a microcontroller USB PD
implmenetation was reset. However, performing this sequence without
coordinating with the analogix driver results in a mismatch of
expectations regarding the internal polarity. The driver already
sets the expected interrupt polarity, but performing this reset
in chipset_pre_init() changes the expected setting which results
in occasional power sequence state machine hangs since
tcpc_get_alert_status() was always returning true. Lastly, added
comment to board_reset_pd_mcu() indicating how that sequence is likely
not needed if it's only invoked in the EC reset path.
Getting the analogix chip out of reset works in conjunction with the
default gpio settings for USB_PD_RST_ODL as well as the implementation
of board_set_tcpc_power_mode().
BUG=chrome-os-partner:53035
BRANCH=None
TEST=Rachel tested with change. Consistent power sequencing completes
without any hangs.
Change-Id: I9ffabaf85f33d6a361caef631e3e6d86c4cf8081
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346733
Reviewed-by: Shawn N <shawnn@chromium.org>
updated the following based on amenia 1.2 hardware change:
gpio change
invert kbd col 2
g782 temp sensor
adc ch0, 2 reading
kx022 base accel
lid gyro/accel/mag i2c port change
bd99955 charger
bc1.2 support (CL:341030)
tcpc support (CL:341535)
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I178baf326c8edd8e0dadac6a6480625177d90a09
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/341534
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Before the change was made, the EC clock will be changed to 16MHz
when wake up from sleep mode, but we need it to keep at 8MHz.
This issue only occurs when EC sleep mode is implemented.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=The 'IT83XX_ECPM_SCDCR3' register keeps default setting.
Change-Id: I206c5e657aba296684d60d6b30ed4071798dd96a
Reviewed-on: https://chromium-review.googlesource.com/345737
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@google.com>
It is not trivial to direct output of this make file into a different
directory, let's just add the byproducts to a local .gitignore.
BRANCH=none
BUG=none
TEST='git status' after running make does not show any junk any more.
Change-Id: Id04822102d788c6883cff36f26fd8f9d50c996aa
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/346746
Reviewed-by: Anton Staaf <robotboy@chromium.org>
The 144-pins package IC(IT8320) supports these two GPIO groups.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Declare GPIO groups K/L in gpio.inc and using console commands
'gpioget'/'gpioset' to read/set GPIOs.
2. Choose four GPIO pins(GPIOK.0/1 and GPIOL.0/1)
and test interrupt functionally.
Change-Id: Ia618c314eeca1d061ffe172da762865f5df9b5c6
Reviewed-on: https://chromium-review.googlesource.com/345776
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@google.com>
Enabled CONFIG_CMD_RTC_ALARM. EC_HOST_EVENT_RTC
is enabled when the rtc_alarm goes off,
alerting the AP to transition from S3->S0.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=rtc_alarm <num> and see event set in ec console
after <num> seconds. Also, check if new bit set
through hostevent command in ec before/after
rtc_alarm goes off.
Change-Id: I53b1705ce0925000f35b9f80752035d198db3310
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/345474
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds the basic framework for Reef including full GPIO listing,
board config file, and rudimentary functionality. It has not been
fully tested and still has several TODOs/FIXMEs. For now we just need
something that will build and can be incrementally improved.
BUG=chrome-os-partner:53035
BRANCH=none
TEST=EC and AP both boot, seems reasonably stable for now
Change-Id: I4934ad00917e251dd1d7eb759207a92c45a36136
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339292
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
LPC access interrupt only enabled when EC entering deep doze mode. This
will reduce interrupt of LPC access. Also, this interrupt is always
enabled for LPC platform to support "CONFIG_LOW_POWER_S0".
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=Tested ectool command 'version' x 10000.
Change-Id: I9053c4018b38a8a852c3c6254e1fcde625f3fa3a
Reviewed-on: https://chromium-review.googlesource.com/336112
Commit-Ready: Dino Li <dino0303@gmail.com>
Tested-by: Dino Li <dino0303@gmail.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Setting NVIC_EN register is not a suitable method if you want to turn
on/off one GPIO's interrupt. Since there're eight sources belong to
the same interrupt, using MIWU_EN register which bit belongs to one
MIWU's source is a better way.
Modified sources:
1. gpio.c: Replace accessing NVIC_EN register with MIWU_EN in gpio's
interrupt utilities.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
Change-Id: I282a45f5a3ab7cb032b2282cf7e92cacc5e706b6
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/342122
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Driver implements TCPC for ANX74xx chips. Enables Type C
port for USB and DP alt mode. Enable port role swap feature.
Driver implements TCPC for ANX74xx chips firmware version 1.0 and later.
Please update to ANX74xx firmware to V1.0 or later version to work.
Change list:
1, modify the position of define and struct declare
which response the comment for patch 22.
BUG=chrome-os-partner:49510
BRANCH=none
TEST=tested compiled binary for pdeval-stm32f072 board with this patch.
Power contract establishment, port role swap, DP alt mode works fine.
Change-Id: Iae6322510605a08d3bdd08446116ef5f9e4f7a7c
Signed-off-by: Aman Kumar <akumar@analogixsemi.com>
Signed-off-by: Junhua Xia <jxia@analogixsemi.com>
Reviewed-on: https://chromium-review.googlesource.com/322433
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
