The public sources look for board configurations in directories
named board/$BOARD/
Sometimes it's necessary to keep sensitive projects out of the
public view for a bit.
This CL allows board configurations to also appear in directories
named private*/board/$BOARD/
BUG=none
BRANCH=none
TEST=manual
First, ebuilds and "make buildall" seem to work just as before.
Second, I copied 24 of the existing boards (those without
board-specific #ifdefs in the code) into a private*/board/
directory, renamed them to something unique, and ran "make
buildall" again.
Both public and private boards compiled and passed their tests.
Change-Id: I977c23cb8e73e40677c8f329abca8bbc51fd53df
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/292428
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Use new board-level hibernate GPIO state function to turn off LEDs in
hibernate.
BUG=chrome-os-partner:43807
TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console,
verify that LED remains off. Press power button, verify that board wakes.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id695df9b5e75514f8f807a894b63f71676b66f92
Reviewed-on: https://chromium-review.googlesource.com/292317
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new board-level function board_get_gpio_hibernate_state which can
optionally be defined to set the desired state of a GPIO during
hibernate.
BUG=chrome-os-partner:43807
TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console,
verify that LED remains off. Press power button, verify that board wakes.
BRANCH=None
Change-Id: Ica11554e231e88773c3e139fea4622377ebe1e42
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/292471
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When flash_set_protect() is called pretend to activate "ALL" protection,
and report it active if asked. This persists through sysjump and cleared
on reboot/reset.
BUG=chrome-os-partner:43323
TEST=Cyan. "flashinfo" should show "all_now", after "flashwp now" called,
but only if WP is active and RO protection is activated earlier
BRANCH=strago-7287.B
Change-Id: I042e5311d79b7ef8e5bc3917662df1edab0e65cb
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/290813
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Modify i2c driver on mec1322 to change from sleeping and waking
on i2c interrupt, to just doing a blocking wait for i2c transfer
to complete. This greatly improves the i2c transaction time on
fast busses.
BUG=chrome-os-partner:43416
BRANCH=none
TEST=test on glados. test can talk to battery and PD MCU. Use
logic analyzer to see delay between bytes during an i2c transfer.
The delay goes from ~70us to ~4us.
Change-Id: Iee2a903d27b2e50e54d64bd6d5ed4920293fe575
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289667
Reviewed-by: Shawn N <shawnn@chromium.org>
Allow more than one SPI master.
Add CONFIG variables to address the system SPI flash.
To have SPI master ports, spi_ports array must be defined.
BRANCH=smaug
TEST=compile
BUG=chrome-os-partner:42304
Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288512
Commit-Queue: David James <davidjames@chromium.org>
Changes for glados proto 2 build. These changes are behind GLADOS_BOARD_V2,
which is not defined by default in order to support existing boards.
BUG=chrome-os-partner:42933
TEST=Verify that Glados v1 board continues to boot AP. Verify
compilation on GLADOS_BOARD_V2.
BRANCH=None
Change-Id: I68634f95f94d3d37f18d676c01219f92b6ddfc45
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/287291
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix hibernate so that plugging a USB-C charger properly wakes the
system. In addition, change the default hibernate behavior to restart
after wake.
BUG=chrome-os-partner:42104
TEST=Run 'hibernate' on Glados. Verify that wakes occur when power
button is pressed, lid switch is toggled, or when a charger is attached
to either USB-C port.
BRANCH=None
Change-Id: I54b8d58e20c35f25883238df24e7f23bb743abaa
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/286660
Reviewed-by: Alec Berg <alecaberg@chromium.org>
The same calculation is used across the code, so move it to a common
macro.
BUG=chrome-os-partner:42104
TEST=Verify Glados still boots AP.
BRANCH=None
Change-Id: I90da348f37fc670971737cfc5ddcfb9c34096c4b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/286169
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Implemented mec1322's heavysleep in idle task to
reduce further EC power down on S3.
MEC1322 needs sleep-enabled for all blocks to
acheive max power down including UART.
Real heavysleep will be effective only when
console/uart is not active.
To enable this commit, board-specific commit is required.
For example, check commit, "Enabling heavysleep idle task at S3".
Test:
1. Put device into S3 mode by typing 'powerd_dbus_suspend" in Linux
shell.
2. wait at least 1 min till EC console sleeps
3. measure EC power.
Since idle task is continuously scheduled, EC will enters/exits
to/from heavy sleep mode frequently in S3 and power consumption
will be changed dynamically.
For acurate power measurement, high-sampling-rate measurement
system might be required and using DMM might not give accurate
number.
BUG=None
TEST=Tested on evt1p0/evt1p7/DVT
BRANCH=None
Change-Id: I435ca347cab2f4d51cefeee802c3bf30fb393fa1
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283603
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
This commit introduces the build infrastructure changes needed for
creating a shared RO library. (libsharedobjs). The end goal is for the
library to contain various objects that can be shared with both the RO
and RW EC images.
Now, there are 3 make goals: ro, rw, and libsharedobjs.
In order for changes that are only specific to a single image (ie: RW
only) to be applied correctly, the object files are now built separately
for the RO, RW, shared objects library targets.
NOTE: Certain EC targets are incompatible with this model due to the
fact that only one image is present within flash at a time.
BRANCH=none
BUG=None
TEST=make -j buildall tests
TEST=make -j BOARD=cr50 xrefs
TEST=make BOARD=samus dis
TEST=Built samus EC image and compared that the final EC image was
identical to the upstream version (except for the git SHAs & version
strings).
CQ-DEPEND=CL:285934
Change-Id: I8e67f089710be9c6d7017718109262394bdad2f5
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/274079
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Fixes cyan/board.h to use correct SPI part
* Adds new flash protection regions in spi_flash_reg.c
* Sets SRP register in flash_physical_protect_at_boot()
* Fixes a bug in COMPARE_BIT macro
* Makes spi_flash_set_status() fail only when both HW pin is asserted
AND SRP(s) are set
* Makes sure set_flash_set_status() completes before returning
BUG=chrome-os-partner:40908
BRANCH=master
TEST=on Cyan:
With WP pin de-asserted:
flashrom -p ec --wp-enable
flashrom -p ec --wp-status, make sure it is enabled
flashrom -p ec --wp-disable
flashrom -p ec --status, make sure it is disabled
flashrom -p ec --wp-enable
Assert WP pin (either with screwdriver or dut-control)
flashrom -p ec --wp-disable
make sure it failed
Change-Id: I338cc906b73e723fdbb37f7c2fd0c4da358b6c8e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276671
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Allow multiple GPIOs to wake the EC from hibernate by requiring boards
to define hibernate_wake_pins and hibernate_wake_pins_used. In addition,
clean up the GPIO-skipping hibernate code, and skip setting PCH_RTCRST
as an input due to a bug on certain boards.
BUG=chrome-os-partner:42104
TEST=Manual on Glados. Run 'hibernate' from EC console, verify that EC
wakes with power button press or with "dut-control lid_open:no".
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I13a6e062393cab8ed7129eda253585951f771109
Reviewed-on: https://chromium-review.googlesource.com/285924
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Mec1322 cannot distinguish between Power-on and reset condition.
MEC1322_EC_WDT_CNT was used to determine the power-on condition.
VBAT_POR cannot not be used to distinguish no battery condition.
All of the feautures that need support need to determine VCC1_REST
which is used for reset considion. lfw and main code use the same
condition.
When VCC1_RESET is asserted we need to set the image type to
RO image for sysjump to work correctly. This in turn will affect
Recovery mode,software sync and Flashrom. All of these conditions
were tested with this patch.
BUG=chrome-os-partner:40526
TEST=Recovery mode,Software Sync,Flashrom
BRANCH=None
Change-Id: I65f2aa9f56863597116b875ea436d4413887b92b
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283605
Reviewed-by: Shawn N <shawnn@chromium.org>
Concurrent SPI transactions are not possible, however in case of external SPI
and flashrom update scenario both host command and vhash trigger transactions.
This adds mutex for the SPI transcation
BRANCH=None
BUG=chrome-os-partner:38103
TEST=on Cyan, run hundreds of flashrom cycles to make sure there are no read,
erase or write errors
Change-Id: If346ebe635387d477dcea5f406a5c31579142e2d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/282113
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reset cause was recorded / corrected only in RO/RW images.
lfw still has old implementation.This caused sysjump RO/RW to
not jump appropriately.
BRANCH=None
BUG=chrome-os-partner:38103
TEST=on Cyan,sysjump RO and sysjump RW console commands
nd make sure it jumps to the right image.
Change-Id: I37138f552fdd385c98d770d242d896ffc014697c
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/282210
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
When RO/RW sysjump is made watchdog is not disabled. Since LFW needs to
load firmware image into SRAM over SPI, there is a certain chance watchdog
counter will fire in the middle of it.
BRANCH=None
BUG=chrome-os-partner:38103
TEST=on Cyan, run hundreds of flashrom cycles and make sure there is no
watchdog reset
Change-Id: Idafcc6a1c9fb35f04be398a68e3ec05bb2b1425d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/282112
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
flashrom on target issues a salvo of flash read commands with small
buffer size (128 bytes). Since there is no yield this starves other
tasks/events including hooks and as result watchdog is never reloaded.
This change makes read function yield to other tasks. In addition,
spi_enable()/disable chaining leads to situations where a SPI can be
disabled in the middle of transcation. This is addressed by keeping
SPI permanently enabled in LFW entry function, as well as in RW/RO
early init functions.
BRANCH=None
BUG=chrome-os-partner:38103
TEST=manual on Cyan, run flashrom -p ec -w xx in cycles, swaping xx so that
flashrom does flash. Make sure there is no watchdog triggered
Change-Id: Id5c50239a1d5c64054d7c660dd03b2be4678221c
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/282111
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
mutex_lock() is called from MEC1322_IRQ_ACPIEC0_IBF
interrupt context, causing deadlock and assertion
in __wait_evt().
In the interrupt context it now checks for mutex lock first.
If the mutex is already locked,, it will disable ACPI
interrupts and defer the memmap mutex lock.
Added LPC interrupt disable/enable functions as needed.
Increased deferred function count where needed.
BRANCH=None
BUG=chrome-os-partner:40820
TEST=Test for suspend-resume, cold, warm reboots and
other general stability.
Change-Id: I3dda0d4635a6b6281faf200c8c7b6fcba8877254
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/280418
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Since the reset cause was not recorded correctly
recovery mode(Esc+Refresh+Power) was not working.
With this change power-on reset state and VCC1_RST# only state
are distinguinshed.
BUG=chrome-os-partner:41479
BRANCH=none
TEST=Esc+Refresh+Power boots to recovery screen
Refresh+Power reboots the system
Change-Id: I63eff488c970302e7afe8a677a57ad27d4d9918e
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/280782
Reviewed-by: Shawn N <shawnn@chromium.org>
This unifies all the EC header files to use __CROS_EC_FILENAME_H
as the include guard. Well, except for test/ util/ and extra/
which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively.
BUG=chromium:496895
BRANCH=none
TEST=make buildall -j
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029
Reviewed-on: https://chromium-review.googlesource.com/278121
Reviewed-by: Randall Spangler <rspangler@chromium.org>
changes added to support flashrom are:
sysjump support to be able to copy the RO/RW image
and jump to it without causing AP to reboot while
its alreday ON.
LPC init should be reinitialized on sysjump
corrected gpio_set_flags_by_mask to make sure we
update the register only for GPIO_LOW condition and not
all else conditions.
BUG=chrome-os-partner:38103
TEST=commands : flashrom -p ec -w ec.bin
flashrom -p ec -r ec.bin
BRANCH=none
Change-Id: I23892f0378d756052030e73034c3acdd41477e34
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/272000
Reviewed-by: Shawn N <shawnn@chromium.org>
Page Boundary.
If SPI Flash write is at an offset within the page and the length
is greater than remainder of the page, the Flash page gets
corrupted as addressing wraps to the beginning of page and
previously written data gets overwritten. This change splits SPI
Flash writes in such cases into two operations in different pages.
BUG=None
BRANCH=None
TEST=During Software Sync, Depthcharge sends Flash write chunks that
cross page boundary. With this change, the RW parition does not get
corrupted. This can be confirmed by executing a successful
"sysjump RW" after a Software Sync.
Change-Id: I46349eea0d8e927353de7cb55a61e9960291adb6
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/275760
Reviewed-by: Shawn N <shawnn@chromium.org>
According to the datasheet, PIN should not be set in the CTRL register.
BUG=none
TEST=Verify with I2C analyzer that no error is observed.
BRANCH=none
Change-Id: Ifed58b413151b40ed951cb71b1164432fea28eca
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276672
Reviewed-by: Shawn N <shawnn@chromium.org>
Charger task is overflowing and causing crash.
Increased charger task stack size by 128 bytes.
Also increased console/hook by 128 bytes as these
are also close to its limit.
BRANCH=None
BUG=chrome-os-partner:40766
TEST=1.Program EC image.
2. Run various tests to verify charger stack doesn't
overflow.
Change-Id: I6e350584508fa3a47769982b1e0cf3e3aea9ded6
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/274204
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Allow timeout to be set at runtime by controller.
BUG=chrome-os-partner:40780
TEST=Manual on Glados. Verify PD I2C communication is functional.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I582e47c7bebfed7a639789c90064d86ffe1a5401
Reviewed-on: https://chromium-review.googlesource.com/274967
Reviewed-by: Alec Berg <alecaberg@chromium.org>
- Don't re-send our slave address if we're not generating a start
condition.
- Handle repeated start vs new transaction properly in the Rx case.
BUG=chrome-os-partner:40677
BRANCH=none
TEST=Manual on glados. Verify 'battery' dumps correct info, and i2cscan
succeeds. Also verify that tcpc communication with PD transmits the expected
data.
Change-Id: I30315d2d82857d6031fda6d4e6a787a52ec01382
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273956
Reviewed-by: Alec Berg <alecaberg@chromium.org>
i2c_xfer was previously implemented at the chip-level, but now we want
to add some global retry logic. Rename the chip-level i2c_xfer functions
to chip_i2c_xfer and add a new global wrapper function i2c_xfer.
BUG=chrome-os-partner:39613
TEST=Run "battery" from EC console on Cyan, verify that values + strings
are correctly printed.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: If37c85cc3cf94fd53feb6931553e10c30ad6cad6
Reviewed-on: https://chromium-review.googlesource.com/272939
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Our existing GPIO macros use port# / gpio#, but the concept of different
GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros
for chips which do not have distinct GPIO ports.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b
Signed-off-by: Steven Jian <steven.jian@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/262841
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Since stm32 and mec1322 now support open-ended i2c_xfer, we can move the
lm4 i2c_read_string implementation to common code and delete all
chip-specific versions.
BUG=chrome-os-partner:39613
TEST=Run "battery" from EC console on Cyan and Oak, verify that battery
info + strings are correctly printed.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I06369df64bb2eb747d163664b4c96eeacb4b1faa
Reviewed-on: https://chromium-review.googlesource.com/272938
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Modify i2c_xfer to support transfers where start and stop conditions are
not issued together.
BUG=chrome-os-partner:39613
TEST=Manual with subsequent commit. Verify that 'battery' shows proper
values + strings.
BRANCH=None
Change-Id: If98c9493902326203880645828061c45c9cfd8be
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/272995
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the
flash footprint of the firmware.
Add additional protection to some functions/data to avoid removal by the
linker when their usage is not obvious.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall (with and without LTO enable on all boards)
Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059
Reviewed-on: https://chromium-review.googlesource.com/271291
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Correct image offsets to reflect our actual layout.
BUG=chrome-os-partner:39741
TEST=Manual on Cyan. Verify EC image boots and FMAP RO_FRID and RW_FWID
point to our actual IDs.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: If0c4e44f45cac1cdc0a99cf0ae4c17e0ead95486
Reviewed-on: https://chromium-review.googlesource.com/270353
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
- Use CONFIG_*_MEM when dealing with images in program memory.
- Use CONFIG_*_STORAGE when dealing with images on storage.
- Use CONFIG_WP when dealing with the entire WP RO region.
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches
actual layout of image. Verify flashrom succeeds flashing + verifying EC
image using host command interface.
BRANCH=None
Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270269
Rename image geometry configs with a uniform naming scheme to make their
purposes more clear.
CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory
CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage
CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image
CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory
CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage
CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image
CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage
CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Set date / version strings to constants then `make buildall -j`.
Verify that each ec.bin image is identical pre- and post-change.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd
Reviewed-on: https://chromium-review.googlesource.com/270189
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Flash read,erase and write should access SPI flash
and not read SRAM MAPPED location.
flashrom -p and Software sync use the same flash functions to
perform flashread,flashearse and flashwrite.So these functions
should be reading RW image starting address offset.Address offset
sent by host should not depend on the actual SPI flash as the EC
code handles the right offset to program the ec.bin(via flashrom -p)
and RW image only via software sync.
BUG=chrome-os-partner:38103
BRANCH=None
TEST=flashrom -p options tested to read and update ec.bin
Change-Id: I3fb16accf3e05eaa3469a8a589962164574d5fb2
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/269231
Reviewed-by: Shawn N <shawnn@chromium.org>
With mec1322's EMI set to decode IO 0x800, it does not have any other
interfaces to support POST code via IO 0x80.
This change is to enable Port80 POST code support via polling method.
Limitation:
- POST Code 0xFF will be ignored.
- POST Code frequency is greater than 1 msec.
BUG=chrome-os-partner:39386
TEST=Verified Port80 POST code is captured in EC console.
Verified "port80 task" console command will disable/enable Port80 task.
Verified "port80 poll" will get the last Port80 POST code.
BRANCH=none
Change-Id: I27e53e84b5be1fd98464a44407dd58b93d8c798d
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/266783
Reviewed-by: Randall Spangler <rspangler@chromium.org>
i2c levels were not reporting correct value as programming the
controller to switch to Bit Bang mode was not enabled.
BUG=chrome-os-partner:39400
BRANCH=None
TEST=Wedge condition was simulated and unwedge was validated using
Oscilloscope
1. SDA was grounded, ran i2cxfer console command,
SCL line creates pulses when SDA gets wedged.
2.SCL was grounded to create cloack stretching, ran i2cxfer console
command and unwedge was confirmed.
Change-Id: Id96d8460820b7d19961ed94d1262112ebd146636
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/267137
Reviewed-by: Shawn N <shawnn@chromium.org>
mec1322 only has 96KB program memory, vs 256KB
flash space on lm4.We no longer have enough program
memory to load both RO and RW at boot. We'll want to
implement a small loader program that will load either
RO or RW from flash, and then jump to the loaded image.
CONFIG_FW_INCLUDE_RO is enabled to include RO image into
the build.
pack.py script is altered to load the (lfw + R)O on boot.
Software sync is not added.Distinguish between
RO/RW is yet to be added.
flash_ec is altered to support padding 0xFFs to 256k ec.bin
to match the size of the SPI flash of the board.
BUG=chromium:37510
BRANCH=None
TEST=Make -j buildall,Verified ec.bin to be 256k.
Verified RW image at offset 0h and (lfw + RO) at offset 2000h.
On boot sysjump to lfw. lfw checks in shared SRAM (currently RO)
and jumps to RO image.
Change-Id: Ib9b114e2f24a615d5e5bd8b3803be621d1e5bd17
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265807
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>
lfw is a customized boot loader with max targeted code size of 4k
and data size of 2k.It supports minimal functionalities required to
support chromebooks RO/RW architecture.It is placed in the
write porected section with RO image .
Capabilities include SPI,DMA,UART with minimal debugging support.
Currently sysjump support is missing and exception handling is very basic.
BUG=chromium:37510
TEST=make buildall -j, flashing and booting on strago
BRANCH=None
Change-Id: I803998d489297dfe0745dcccbb54412035d73f78
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265904
Reviewed-by: Randall Spangler <rspangler@chromium.org>
