Currently, the only way to prevent a system from hibernating is via the
EC console command "hibdelay". This commit adds the host command
equivalent so that it can be set elsewhere. The host command takes the
amount of time in seconds to delay hibernation by and responds with the
current time in the G3 power state, the time remaining before
hibernation should be invoked, and the current setting of the
hibernation delay.
BUG=chrome-os-partner:45608
BUG=chrome-os-partner:44831
BRANCH=None
TEST=Build and flash on samus. Issue the host command from EC
console. Verify that the hibernation delay was updated by checking with
the hibdelay command.
Change-Id: I34725516507995c3c0337d5d64736d21a472866c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/302197
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Modify the GPIO seeting according to the Oak rev4 schematic.
BRANCH=none
BUG=none
TEST=manual
Confirm all reversion of oak can be built pass:
make -j EXTRA_CFLAGS=-DBOARD_REV=4 BOARD=oak
make -j BOARD=oak clean
make -j EXTRA_CFLAGS=-DBOARD_REV=3 BOARD=oak
make -j BOARD=oak clean
make -j EXTRA_CFLAGS=-DBOARD_REV=2 BOARD=oak
make -j BOARD=oak clean
make -j EXTRA_CFLAGS=-DBOARD_REV=1 BOARD=oak
Change-Id: Ib1051f29df9d1919f0ae3ecaf55dc0997ea29c3e
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/300728
Reviewed-by: Rong Chang <rongchang@chromium.org>
since we add debounce time (50 ms) for SUSPEND & POWER GOOD signal
after oak rev3 (commit e58a913b). It will causes the chipset_reset
function failure, because PMIC_COLD_RESET_L_HOLD_TIME is short.
PMIC_COLD_RESET_L_HOLD_TIME should be greater than 100 ms
[SUSPEND_DEBOUNCE_TIME (50 ms) + POWER_DEBOUNCE_TIME (50 ms)].
So, revise PMIC_COLD_RESET_L_HOLD_TIME to 120ms.
And, using hook to avoid blocking the EC console when executing
"apreset" EC console command.
BRANCH=none
BUG=chrome-os-partner:44955
TEST=manual
Run EC console command, after AP enter S0:
> apreset
AP should be reset normally.
Change-Id: I04e31aef8be3092ad39b5f1b1c2b75b78b4d1d7b
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/299625
Reviewed-by: Rong Chang <rongchang@chromium.org>
Since the firmware_ECPowerButton testcase holds down power button
about 10s to shut down without powerd, we set DELAY_FORCE_SHUTDOWN
about 8s to make sure the powerbutton is pressed long enough to
force shutdown.
BRANCH=none
BUG=chrome-os-partner:43412
TEST=manual
run "firmware_ECPowerButton" testcase on rev3.
Change-Id: Ib41cdecfa0342236d618e6fdffcb64bf7f51b557
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/296884
Reviewed-by: Rong Chang <rongchang@chromium.org>
Enable the support for limiting the inrush current by routing the PCH_SLP_SUS
through EC gpio PMIC_SLP_SUS which allows the DUT to boot on charger without
the battery / dead battery. This is applicable to Kunimitsu FAB4 only.
Enabling the Glados patch for Kunimitsu FAB4.
Change-Id: I55de857f7006777640f7853b7bde98ba97e8bd13
Reviewed-on: https://chromium-review.googlesource.com/287378
BUG=chrome-os-partner:44706
TEST=FAB4 prototype boots to UI without battery / dead battery.
BRANCH=none
Change-Id: Ie81cdf3c59fc02d6d59dd06ca321705ca06e7b88
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/296521
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
(refer to CL:273620) enable the MKBP event feature to send host event
and wire up the PD specific events.
But, CONFIG_MKBP_EVENT conflicts with CONFIG_KEYBOARD_PROTOCOL_MKBP,
due to the GPIO name of EC interrupt pin. Align the GPIO naming of EC
interrupt pin to EC_INT_L.
BRANCH=none
BUG=chrome-os-partner:44643
TEST=On Oak rev3, plug/unplug USB devices and add kernel trace to see
the PD events happening.
Change-Id: I10de9c6611583bb6165bdc1848e542d4b8bba954
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/296012
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
If the power button is pressed while S5 inactivity timer is about to
expire, EC need to give CPU a little time to start up before changing
the state from S5 to G3 (the hard off state); otherwise the system will
not start up. This issue can be reproduced on Rambi.
BUG=chrome-os-partner:42728, chrome-os-partner:42811
BRANCH=None
TEST=Implement an ec command to simulate power button press while S5
inactivity timer is about to expire, and then make sure that the
patch did solve the issue.
Change-Id: I022e8e14fd41447898760a4d57a4702e2c00a0d5
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/290280
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296436
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On skylake the apshutdown command holds the power button asserted until
the power state machine decides to deassert the power button. Previously
this check was taking place in G3 state. As such when the board waited
in S5 for 10 secs one couldn't re-power on the system. To alleviate that
move the logic for power button deassertion into the S5 state.
BUG=chrome-os-partner:44532
BRANCH=None
TEST=Used apshutdown. When device got to S5 power noted another
powerb command would bring the system back up instead of waiting
to enter G3 power state.
Change-Id: I9989b27bd48819d7c3e5efd071b0327c38fe91e2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295198
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The internal keyboard and trackpad must be disabled in tablet mode to
prevent unwanted input.
BUG=chrome-os-partner:44305,chrome-os-partner:40849
TEST=Manual on Glados. Boot system with lid open, verify that keyboard
is functional and ENABLE_TRACKPAD is high. Swing lid to tablet mode,
verify that keyboard is not functional and ENABLE_TRACKPAD is low.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9f250ae82963c8b497de991b6cce52c86841d08a
Reviewed-on: https://chromium-review.googlesource.com/295206
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=none
TEST=Used "shutdown -h now" Kernel console command to test on Kunimitsu.
With only battery after 1 hour, device enters to Pseudo G3 and the
V3p3A is off. With AC connected, device is in G3.
BRANCH=none
Change-Id: I955662eb69ac608e9b2d12bdcfbc1258ca83f3a5
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are a number issues with the current skylake power
sequencing. First, SLP_SUS_L was not being honored from
the chipset when a deep S5 or S3 was requested. Additionally
the BATLOW_L signal was being used to block the chipset from
waking which caused a race in waking from deep S5 that required
an additional pulse of the PCH_WAKE_L signal instead of the
chipset seeing the power button event. Another issue is that
POWER_S5 state was being completely bypassed so any global
resets that brought down SLP_S4_L caused the state machine
to enter into G3 state.
The code was changed to remove BATLOW_L usage, PCH_WAKE_L
in the POWER_G3S5 state, and SLP_SUS_L is honored in the
non POWER_S5G3 and POWER_G3 state. That allows SLP_SUS_L
pass-thru to work on glaods. Lastly the code was reorganized
to accomodate the above change without sprinkling them
throughout the state transitions.
BUG=chrome-os-partner:44081
BUG=chrome-os-partner:44082
BUG=chrome-os-partner:43475
BRANCH=None
TEST=Built and booted glados. Deep S3 and S5 wakes work. Fresh
flash plus a global reset doesn't bring the system down to G3.
Change-Id: Id1d7af1b6a733a9db5aad584950da8ab5898ea83
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293844
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The system will not wake from Deep S5 if BATLOW# is asserted,
so wait for that to deassert, then pulse the wake pin and wait
for SLP_SUS_L to deassert.
BUG=chrome-os-partner:43545,chrome-os-partner:44079
BRANCH=none
TEST=verified on P2 board
Change-Id: I3b36159b574d418c9b79c478d0a41f753474fa6a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293595
Reviewed-by: Shawn N <shawnn@chromium.org>
Switch to V2 glados as the default, and remove support for V1.
BUG=chrome-os-partner:43075
TEST=`make buildall -j`
BRANCH=None
Change-Id: I58f33225177d259916e8877084c2c431922e7bc5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293303
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In case of 'apshutdown', during transition to S5 state,
GPIO_PCH_SLP_S4_L signal was not getting deasserted but
required rail went away (GPIO_PCH_SYS_PWROK). So it was
going on a loop S5 -> S3 and S3 -> S5.
In strago GPIO_PCH_SYS_PWROK is the PMIC_EN GPIO and hence
conditinally setting it based on CONFIG_PMIC
BUG=none
TEST=apshutdown on strago
BRANCH=none
Change-Id: I9c581a3dfcb9cc84a22b41505e7df496d72d5f4c
Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com>
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292024
Reviewed-by: Shawn N <shawnn@chromium.org>
There are 3 methods to power on the system:
1) Pulling PWRKEY low (User presses PWRKEY)
2) Setting BBWAKEUP high
3) Valid charger plug-in
We should ensure that BBWAKEUP should be high when release PWRKEY.
Due to the RTC driver of coreboot will move to ramstage, and the
setup timing of BBWAKEUP will be postpone. In order to ensure PMIC
keeping the power until coreboot pull BBWAKEUP up, it needs to
increase the PMIC power key press time to avoid PMIC turn the
power off. This change is related to:
https://chromium-review.googlesource.com/#/c/257389/
BRANCH=none
BUG=none
TEST=manual
Update coreboot with above patch, press power key and system
should power on normally.
Change-Id: I7fabc49e0b3956885cb83a0b40c31c60080d0cbc
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/290538
Reviewed-by: Rong Chang <rongchang@chromium.org>
The AP warm reset pin is changed from rev3 of oak board.
PB3 is stuffed before rev3 and connected to PMIC RESET pin to
reset the AP. For rev3, the AP reset mechanism is changed:
PC3 connects to PMIC SYSRSTB, pull PC3 to low, to reset AP.
BRANCH=none
BUG=none
TEST=manual
1. define CONFIG_BOARD_OAK_REV_2 in board.h
make -j BOARD=oak
2. define CONFIG_BOARD_OAK_REV_3 in board.h
make -j BOARD=oak
both cases should be built successfully and run "apreset" command.
AP should be reset normally.
Change-Id: I979e93acf755509f8cb7a12dd77eb7c9e7a98ccc
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/289476
Reviewed-by: Rong Chang <rongchang@chromium.org>
In S3, the EC isn't expecting AP host commands, so it's safe to enable
sleep
BRANCH=none
BUG=none
TEST=Check sleep mask in S0 and S3.
Also check sleep mask after sysjump with AP on and with AP off.
Change-Id: I9dcfe996e8e92e6703d71bbe966cd2447c6b14fe
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/290002
Reviewed-by: Rong Chang <rongchang@chromium.org>
In order to pass the test case "firmware_ECPowerButton",
I change the value of DELAY_FORCE_SHUTDOWN from 11s to 10s.
The test case holds down power button about 10s to shut down
without powerd.
BRANCH=none
BUG=none
TEST=manual
run "firmware_ECPowerButton" test case.
Change-Id: I3da93769f1cb52b04c447df9a7795d3c28ab2bf0
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/282153
Reviewed-by: Rong Chang <rongchang@chromium.org>
Now that HOOK_INIT hooks are called from a task switching context, most
calls to task_start_called() should no longer be needed. This commit
removes them.
BRANCH=None
BUG=chrome-os-partner:27226
TEST=make -j buildall tests
TEST=Flash EC image onto samus and verify EC boot, AP boot, keyboard,
lid, and tap-for-battery all functional.
TEST=Flash EC image onto samus_pd and verify charging still works.
TEST=Flash EC image onto ryu(P3) and verify that EC boot.
TEST=Added ASSERT(task_start_called()) to the places where I removed
task_start_called(). Booted samus, samus_pd, cyan, and ryu with AC
inserted and verified that no ASSERT's were hit upon boot.
Change-Id: Ic12c61862e85ca3a0a295beedbb4eeee6d5e515b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/285635
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Inhibit AP power-on through the BATLOW pin, even if the system is
unprotected, until our charger and current limit are initialized.
Note that this feature is only functional on glados v2 since other
skylake boards do not have BATLOW connected.
BUG=chrome-os-partner:41258
TEST=Manual on glados v1 with rework. Remove battery and attach Zinger.
Verify EC powers on and AP doesn't boot. Run `powerbtn`, verify that AP
boots. Remove all power and attach battery, verify that EC powers on
and AP boots. Also verify compilation on glados v2.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I55de857f7006777640f7853b7bde98ba97e8bd13
Reviewed-on: https://chromium-review.googlesource.com/287378
Check IN_POWER_GOOD signal in S0 and go to S3 if IN_POWER_GOOD is lost.
Finally it will go to S5(G3).
Check suspend and power good signal after POWER_DEBOUNCE_TIME to
avoid transient state.
BRANCH=none
BUG=none
TEST=manual
Test power related commands such as "shutdown -P now" or "apshutdown".
Change-Id: Ia06fc7d8334c0dfbb0263474f57e4dca7313d331
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/282680
Reviewed-by: Rong Chang <rongchang@chromium.org>
Changes for glados proto 2 build. These changes are behind GLADOS_BOARD_V2,
which is not defined by default in order to support existing boards.
BUG=chrome-os-partner:42933
TEST=Verify that Glados v1 board continues to boot AP. Verify
compilation on GLADOS_BOARD_V2.
BRANCH=None
Change-Id: I68634f95f94d3d37f18d676c01219f92b6ddfc45
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/287291
Reviewed-by: Alec Berg <alecaberg@chromium.org>
BUG=none
TEST=Enabled the config and tested on Kunimitsu.
Enter "shutdown -h now" form the Kernel console.
Device goes to Sleep mode in G3 and charger LED turns off.
BRANCH=none
Change-Id: I962018dcfac2998ee0a11784adeceb09931b930d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/286781
Reviewed-by: Shawn N <shawnn@chromium.org>
- Disable USB, wireless and audio power rail when powering down from S3
- Disable sensor power rail and display backlight when powering down
from S0
BUG=chrome-os-partner:42104
TEST=Manual on Glados. Boot AP, verify that display backlight and USB
are functional.
BRANCH=None
Change-Id: I2879f57db555753b280e785df3d2cc967c152f21
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/285545
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Removed USB enable/disable as it will be handled by
HOOK task as CONFIG_USB_PORT_POWER_SMART is enabled.
BUG=none
TEST=Verified on Acer EVT GPIO USB1_ENABLE and USB2_ENABLE value
changed when state switch between S3 and S5.
BRANCH=none
Change-Id: I85f2047c1a40aebf36743a17d353ff3bc481d867
Signed-off-by: li feng <li1.feng@intel.com>
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283593
Reviewed-by: Shawn N <shawnn@chromium.org>
The suspend signal from SoC of oak should be kept at least 50ms.
Add a debounce time for suspend singal detection, to avoid transient
state during SoC boot up.
BUG=chrome-os-partner:42023
BRANCH=none
TEST=plug PD power adaptor to type-c port C1,
The keyboard should be worked (Ensure EC communication is oaky)
Change-Id: I4a6bb4e8ba9d417fe2a3045846d38b2129516d78
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/282471
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
In S3, the EC isn't expecting AP host commands, so it's safe to enable
sleep.
BRANCH=Ryu
BUG=chrome-os-partner:36918
TEST=Check sleep mask in S0 and S3.
Also check sleep mask after sysjump with AP on and with AP off.
Change-Id: I67f0634631f62ee571e18d2870cd4a6926d4e090
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/251750
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Add the console command "power on/off" for AP power on/off.
BRANCH=none
BUG=none
TEST=manual
enter "power on/off" in the ec console to turn AP power on/off.
Change-Id: I16d2af72bc1bf045e7672acd9471dff0a672aff5
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/280957
Reviewed-by: Alec Berg <alecaberg@chromium.org>
According to spec, RSMRST shouldn't be deasserted until 10ms after power
signals become active.
BUG=chrome-os-partner:41556
TEST=Manual on Glados. Verify that AP boots to S0 on power-on, goes to
G3 on apshutdown, and back to S0 on powerbtn.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0acc897fff7c18ad83fc87734569ec7639ae5cf4
Reviewed-on: https://chromium-review.googlesource.com/280571
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
If the AP is already shutdown, apshutdown would previously power the AP
up with a power press. Fix this by making sure we're not already in G3
before triggering the power press.
BUG=chrome-os-partner:40677
TEST=Run 'apshutdown' on glados while in G3, verify that AP does not
power up.
BRANCH=None
Change-Id: I8b898b034dcf40f0acef4fb6098af0aebba566c6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277400
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Now that we've removed boards from ToT, also delete board-specific
code used only by the removed boards.
There are still more things to remove (unused charging chips, LED
drivers, COMx support). More CLs coming.
BUG=chromium:493866
BRANCH=none
TEST=make buildall -j
Change-Id: Ie6bdeaf96e61cadd77e3f6336c73b9b54ff4eabb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276524
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Holding the power button is currently the best known way to bring the AP
back to a state where it is shutdown and not powered.
BUG=chrome-os-partner:40826, chrome-os-partner:40677
TEST=Run `apshutdown` on glados, verify that power state machine transitions
to G3 after several seconds. Run `powerbtn`, verify that state machine
transitions back to S0.
BRANCH=None
Change-Id: Ia799c5f199127f31bd24907b93946c6289d381f8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/275060
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change is necessary to ensure power-up of edge-case Skylake parts.
BUG=chrome-os-partner:40677
TEST=Manual on Glados. Boot system to S0, run "i2cxfer r 4 0x60 0x38",
verify that 0x7a is read.
BRANCH=None
Change-Id: Id9e62731aaa75fb2357a05d898ba2d4d28f87d9e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274114
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
PCH_SLP_SUS_L can take up to 29ms to be deasserted after power-on or
RTC reset.
BUG=chrome-os-partner:40677
BRANCH=None
TEST=Manual on glados. Power board, verify that state machine
transitions to S0. Run "reboot" on EC console, verify that state machine
again transitions to S0.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I3f6e89eee1190a3fe84fdc7d939c05dfe5b94953
Reviewed-on: https://chromium-review.googlesource.com/274077
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Always enable these signals to help debug power sequencing. We'll need
to revert this change later.
BUG=chrome-os-partner:40677
BRANCH=none
TEST=sequence to S0 on glados and stay there
Change-Id: Ia845532fe7aed71bcb42b4ca6a9bfa20aa9e3e00
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273900
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change will help us to debug power sequencing and will likely need
to be reverted later.
BUG=chrome-os-partner:40677
BRANCH=none
TEST=sequence to S0 on glados and stay there
Change-Id: I85d1f0f97a3c93cf26c766a749feb23f9cf4ac62
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273680
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add initial support for Oak rev1 board. This is just the
EC and includes battery charging but does not include
USB PD.
BUG=none
BRANCH=none
TEST=load on oak board and get console
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Change-Id: I626f3921025fbc39ba22b04eeb6dd1084cd70777
Reviewed-on: https://chromium-review.googlesource.com/261678
Debounce time for the GPIO SYS_RESET_L is 16ms hence increased the time
delay between SYS_RESET_L pin toggling to 20ms.
BUG=chrome-os-partner:40246
TEST=Tested "apreset cold" EC console command on Kunimitsu
BRANCH=none
Change-Id: If17229ce485de708b550ec84939e2696e451cb0c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/270776
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The same code exists in four (soon to be five!) different power
sequencing drivers, so move it up to common.
BUG=None
TEST=Manual on Samus. Run "pause_in_s5 on" on EC console, verify that
system stops in S5 on shutdown. Run "pause_in_s5 off" on EC console,
verify that system again goes to G3 on shutdown.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaf05ef7ce017be4f9d173e83e985a7a879ba278c
Reviewed-on: https://chromium-review.googlesource.com/269566
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The USB power is off in S5 with previous ChromeBook.
The braswell platfrom should be the same as before.
BUG=chrome-os-partner:39507
BRANCH=cyan
TEST=The usb power is off in G3/S5 and is on in S3/S0 by ec console.
Change-Id: I719f213a9eb0180f7e95e4c2717c038c79ef56fe
Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/267451
Reviewed-by: Shawn N <shawnn@chromium.org>
The current power sequencing would shutdown the system
when suspend command or reboot was initiated from the kernal.
Proper transitions from S0-S3 and S3-S0 are handled.
BUG=None
BRANCH=None
TEST=Tested on Braswell reference design. Issued
commands from kernel:For shutdown - "shutdown -P now" and
suspend - "powerd_dbus_suspend"
Change-Id: I7cc734f29c0dca89f7d9564f175895467b405df0
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265091
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Eric Caruso <ejcaruso@chromium.org>
When shutting down the MAX77620 PMIC by asserting its SHDN pin, the
EN_PP3300 output of the PMIC (GPIO3) is not driving low keeping the PP3300
rail up. Workaround that issue by removing the pull-up on EN_PP3300 when
we assert SHDN.
Revert the previous CL 263958 aka "ryu: workaround MAX77620 shutdown issue",
in order to use a better workaround which ensures that the power rails
sequencing at startup
Detect the PP1800 rail going up and down by reading the HPD_IN gpio
state (which has a pull-up tied to PP1800), then enable/disable
EN_PP3300 in sequence.
The code using an interrupt on HPD_IN is enabled only on P5,
and as a downside, it is killing the base charging on those boards.
Indeed HPD_IN(C1) is hijacking the EXTINT1 which used to be connected
to the LID_OPEN (E1) GPIO used for the base detection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:38689
TEST=on both P4 and P5 boards, do various power cycling sequences of the
AP using the "apshutdown" and "powerbtn" commands.
Change-Id: Icad6e9ae6a08d76cbfd19f97dd7c129bf43037d8
Reviewed-on: https://chromium-review.googlesource.com/265186
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
