This just adds a .gitignore entry so that git doesn't complain
about the executable you may have built in the extra/usb_console/
directory.
BUG=none
BRANCH=none
TEST=make buildall
This has no effect on the EC code at all. The things in the
extra/ directory are optional and unsupported.
Change-Id: Ib4915f712f9d14caf7418ef4b03aa41e8764fd36
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310840
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reduce system stack size from 4096 to 1024.
Increase code RAM size to 104K and reduce data RAM size
to 20K.
BUG=chrome-os-partner:45690
BRANCH=None
TEST=Tested on Kunimitsu
1. Flash EC, boot up, force to S5/G3, back to S0;
and powerd_dbus_suspend to S3, all work fine.
2. Use console command to dump system stack memory values,
the size used is around 350, >600 still available.
Change-Id: Ib004678cc16f10c94c333063b728a2816ed5b3c5
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/310581
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
LED activity is triggered by HOOK_SECOND. Updated value of led
constants to make sure blinking interval is correct.
BUG=chrome-os-partner:47243
BRANCH=none
TEST=Verified on Kunimitsu battery LED blinks at interval expected.
Change-Id: Ibd1089f3c12b1f449d81aeee9cf430981ae214ea
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/310545
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
1. refer to commit 8bd44bf4, oak has similar issue:
if power good is lost and the power button still press, we need
cancel the long press timer, otherwise EC will crash.
2. Furthermore, EC will crash too if long press timer is still active
during entering S3.
3. The debounce of suspend & power_good signal can be removed on rev4
because rev4 doesn't adopt level shifter.
BRANCH=None
BUG=chrome-os-partner:46857
TEST=Manual
1. press power button during coreboot, and it can shutdown normally, or
2. run test case:
> test_that -b oak <DUT IP> firmware_FwScreenPressPower
Change-Id: I584d8beeb31b6c01289bfe4790453a4a3bd35b1c
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/309942
Reviewed-by: Rong Chang <rongchang@chromium.org>
When building EC image, in the majority of cases the RW and RO images
are built from exactly the same set of object files, and the RO set of
objects is used as a template to derive the RW set of objects.
This is not necessarily correct in all cases, let's just create an
abstract set of object files and use it to derive the sets for RO, RW
and sharedlib as appropriate.
BRANCH=None
BUG=chrome-os-partner:43025
TEST=tested as follows:
- changed the Makefile to sort all object files in a single list
(instead of sorting them by directory, with the directory list
unchanged). Built all targets, saved all .smap files. Then applied
this change and again built all targets. Compare all smap files,
there were no differences.
- modified board/samus/board.h to trigger building sharedlib
objects, verified that build/samus/sharedlib built fine.
Change-Id: Ie563aca62028cae9e16f067ba20b5e2930355cf5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310389
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This has been bothering me literally for years: once in a while there
would be tons of files in /tmp directory named tmpXXXXXX where XXXXXXX
is some random string.
Finally, it became clear that the files are generated when 'make
buildall -j' is called in the ec directory. Next step - it looks like
one of the culprits is building for board named 'chell'. Indeed, this
board uses its own version of cmd_obj_to_bin make function, which,
among other things invokes the pack_ec script to pack the image.
The script was creating temporary files and leaving them behind.
This patch makes the name pattern of the temp files better
recognizable, juts in case, and makes sure that the files are deleted
once they are not needed.
BRANCH=none
BUG=none
TEST=invoking 'make buildall -j' still succeeds but does not result in
leaving temp files behind.
Change-Id: I50c511773caa87d4e92980c4c9a36768b0c3101f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310586
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Make oak_pd a sym link to glados_pd. A few small changes
necessary to make this possible:
- glados_pd now sets the VBUS present power status bit as oak_pd
does and as is appropriate for TCPCI spec.
- oak_pd now has watchdog enabled (not sure why it was
previously disabled).
- add a flag in gpio.inc to define EC_INT pin on B5 for oak_pd
and A14 for glaods_pd (and all other boards pointing to
glados_pd). Note: this breaks oak board rev 1, where EC_INT was
on A14.
BUG=none
BRANCH=none
TEST=make -j buildall
Load on glados and make sure zinger works.
Change-Id: I28f4ee106e44e2819919f1826508fc1fc05bb2a1
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310193
Drop permissions as soon as initialization
is complete. APP code is expected to run
at MEDIUM permission level.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=serial shell starts up
Change-Id: I181d55ca96eb5998ad49856af9f82afb67b03024
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/309919
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Before Oak rev4, it defines 2 wakeup source EC_WAKE(PA0), EC_PWR_BTN_L(PB5).
Due to the wakeup source limitation of STM32F0 (http://goo.gl/VQk9GV),
Oak can only use one wakeup source, because EC_PWR_BTN_L is low-active and
it is kept high always. The HW & SW should be changed after rev4:
Using PA0 as wakeup source only, instead of both (PA0 & PB5).
BRANCH=none
BUG=chrome-os-partner:46670
TEST=Manual on oak rev4 with HW rework.
Detach PD power adapter, run 'hibernate' on EC console, make sure that both
EC and PD go to hibernate, verify the following cases individually:
1. Press power button and verify that both EC and PD wake.
2. Plug PD power adapter and verfy that both EC and PD wake.
Change-Id: Ief37aa1f11a84dd358875f22fa35c484b10bc388
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/309246
Reviewed-by: Rong Chang <rongchang@chromium.org>
Some chips previously defined CONFIG_I2C and others didn't. Standardize
the usage by removing CONFIG_I2C from all config_chip files and force it
to be defined at the board level. Also, make boards define
CONFIG_I2C_MASTER and/or CONFIG_I2C_SLAVE based on the I2C interfaces
they will use - this will assist with some later cleanup.
BUG=chromium:550206
TEST=`make buildall -j`
BRANCH=None
Change-Id: I2f0970e494ea49611abc315587c7c9aa0bc2d14a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310070
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Warm reset key from servo board lets the POWER_GOOD signal
deasserted temporarily (about 1~2 seconds) since Oak rev4.
In order to detect this case, check the AP_RESET_L status,
ignore the transient state if reset key is pressing.
BUG=chrome-os-partner:46655
BRANCH=none
TEST=make buildall -j;
Press warm reset key of servo board, AP should reset normally.
Change-Id: Ib9f111d2273cde61354e72367fe74d4ee15d2291
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/307201
Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-by: Rong Chang <rongchang@chromium.org>
The default battery type of Oak is 3S, in order to compatible to
2S battery, set the minimum voltage of battery to 6V rather than 9V.
BRANCH=none
BUG=chrome-os-partner:46540
TEST=manual
1. connect 2S battery to rev4
2. check the battery info with EC command:
> battery
3. confirm the voltage of battery is match to setting of battery_info.
Change-Id: Ieb7e39817bb0cefa523f73039b68943adb50f045
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/306381
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
1. To enable INT_PRI (hardware interrupt priority level 0~3)
register, bit0@INT_CTRL = 0.
2. GIE need to be enabled before UART is initialized.
[symptom]
To define CONFIG_RWSIG / CONFIG_RSA / CONFIG_SHA256, then power on:
after RW image is verified, firmware stuck in uart_flush_output().
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. bit0@INT_CTRL = 0.
2. The RW image is verified and jump to image RW.
Change-Id: I393a3d5f87ea257885b872c91bfce43aecbaea8b
Reviewed-on: https://chromium-review.googlesource.com/309400
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
[irq]
1. The chip_init_irqs() function clears all IERx and EXT_IERx registers.
[jtag]
2. Enable debug mode through SMBus.
[system]
3. remove console_force_enabled functions.
4. implement __no_hibernate, scratchpad and nvcontext functions.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chrome-os-partner:23575
TEST=1. IERx and EXT_IERx registers are all cleared after chip_init_irqs().
2. console command "scratchpad" and "hibernate".
3. bram bank0 index 0x10 ~ 0x1F (16 bytes) for
system_get_vbnvcontext() and system_set_vbnvcontext functions.
Change-Id: If044d50c69ae80b013ab646a3a6931cec7560ec4
Reviewed-on: https://chromium-review.googlesource.com/309390
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Create two state machines SMB_WRITE_SUSPEND and SMB_READ_SUSPEND to handle i2c
master stall bus and call i2c_xfer again. Notice we should disable i2c
interrupt since cannot read/write SDA reg to clear interrupt pending bit.
Modified drivers:
1. i2c.c: Modified to handle calling i2c_xfer twice or more.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I781f6f8227867ea9c0e265b3064f48602c0f5f07
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/309381
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Enable USB PD logging.
BUG=chrome-os-partner:45933
BRANCH=none
TEST=make -j buildall
make -j BOARD=glados tests
Load on glados and test that PDLOG events show up in dmesg
Change-Id: I61dbc5019ea3228542c2c244228bbb483cf51ead
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/309881
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
I2C1 may be clocked by HSI or SCLK. I2C2 is always clocked by PCLK.
Therefore, apply different timing register values according to the
selected clock source for a port.
BUG=chrome-os-partner:46188
BRANCH=None
TEST=Manual on glados_pd. Verify slave i2c communication is functional.
Change-Id: Icd2306d25d5863b0fc3379e46885a227efb23cca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/309781
Commit-Ready: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
This patch updates the EC codebase to match the latest USB build which
now provides ability to programatically tell between different FPGA
flavors. It also changes the polarity of the 'cold bootsrap' pin, so
using the latest spiflash utility is mandatory.
Note that there has been no signer changes.
BRANCH=none
BUG=none
TEST=as follows:
- programmed the FPGA, it now reports the following when reset:
FPGA |20151029_041713@78167
- booted the new image using the latest spiflash version. Note
that the bootrom now reports the FPGA image it comes from
- disconnected the FPGA upgrade port, rebooted the device, entered
on the device console:
> spstp off
> spste
run on the workstation:
$ examples/spiraw.py -l 10 -f 800000
FT232H Future Technology Devices International, Ltd initialized at 857142 hertz
and observe on the DUT console:
Processed 10 frames
rx count 11574, tx count 5497, tx_empty 10, max rx batch 11
>
Change-Id: I66596061731d9abcf41c5f5984ac479bbc1648e8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/309963
Commit-Ready: Vadim Bendebury <vbendeb@google.com>
Tested-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-by: Ewout van Bekkum <ewout@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Define CONFIG_USB_PD_LOW_POWER by default to save power on both
TCPM and TCPC side by waking PD task less often when possible.
BUG=none
BRANCH=none
TEST=test on glados and samus.
Change-Id: I04441fb8339652cf073689177175a98f28807897
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/309311
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Added more improvements to power consumption when using
CONFIG_USB_PD_LOW_POWER. On the TCPC, when this option is
defined, then decrease the PD task wake interval when
we are presenting Rd, we don't have a connection, AND we
haven't dual-role toggled recently. This shouldn't affect
connection time because we will get an interrupt when VBUS
is detected.
Note: we can't use the low power task wake interval when
we are connected because we need to monitor CC line for
Rp change and we can't do this when we are presenting Rp
because we need to quickly detect loss of Rd.
BUG=chrome-os-partner:45010
BRANCH=none
TEST=tested on glados. verified we connect to a charger in
S0 and S5. and verified that in S5, we spend >99% of our
time in deepsleep (as measured by idlestats console command).
note, that when testing EC and PD must both define
CONFIG_USB_PD_LOW_POWER to get maximum power improvements.
Change-Id: I661110cc7021f6d17937688787ea4f5f4b82973d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/309310
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There is a race condition between SYSJUMP and function
release_pmic_pwron_deferred().
Process of EC SW Sync will delay the execution time of
release_pmic_pwron_deferred(). PMIC will shutdown the power, if
PMIC power button can not be released within 8 seconds (depends
on PMIC spec). In order to ensure PMIC power button will be
released in time, just release it after SYSJUMP.
BUG=chrome-os-partner:46392
BUG=chrome-os-partner:46656
BRANCH=none
TEST=make buildall -j;
Enable EC SW sync and normal mode in coreboot,
Kernel should bootup successfully.
Change-Id: I45d4aa0f0d4280e68282ea11ccfda05201f88aae
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/307220
Reviewed-by: Rong Chang <rongchang@chromium.org>
Lars: enable USB-A port power control
dumb mode is used since lars ec only have control over
the two usb-a ports' power enable/disable functionality.
BUG=none
BRANCH=lars
TEST=Run "make -j BOARD=lars", "make -j BOARD=lars_pd" and
"make buildall -j" to build code and ec.bin can be generated.
Change-Id: I0231b36e3875b56bc822dbae1de37da2182e5736
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/309005
Commit-Ready: 志偉 黃 <David.Huang@quantatw.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Call shutdown() entry point at init() and remove duplicate code.
shutdown would init the sensor so they would be ready if needed.
Set S5 flag to include G3 (hard off) state, not only S5 (soft off).
BUG=chrome-os-partner:45722
BRANCH=smaug
TEST=When doing a RO->RW transition while AP is in G3, check the sensors
are initialized properly. This issue was found while testng the magic
sequence code.
Change-Id: I647f83580240bf5ba0c340fca3184220abe4c12e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308561
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If init of the light sensor fails (for instance, the chip is not present
on the i2c bus), we need to fail the init of the proximity sensor.
Otherwise, the EC will report an unexistent sensor to the AP.
BRANCH=smaug
BUG=chrome-os-partner:46638
TEST=check the proximity sensor is not reported if sensor is disconnected from the
main board.
Change-Id: Ie6b1d74eaac4d6c38d52641626966b5d3ce63bd3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308560
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If init() is interrupted while we are setting the link to the compass,
the BMI160 may be in paging mode and will only answer to registers 7Eh
and 7Fh. Other registers access will return 00h.
To get out of this state, run the sequence to move back from the paging
mode in the error handler. If successful, a subsequent call to init()
will work.
BRANCH=smaug
BUG=chrome-os-partner:45722
TEST=use a special firmware that exists in the middle of the compass
init sequence. Check that the FIFO and all other registers return 0.
Issue 'accelinit 1' (to reset the Gyro): the command succeeds and the
accelerometer is operational again (double tap works).
Check the sequence can be issued after sysjump to RW/RO.
Change-Id: I3455a8cbdcf1c88699ae90f7c09e4438e1268d47
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308184
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add support for two new configs to specify critical energy battery
percentage and critical external charger power. When we are under both
thresholds, set the LIMIT_POWER charger parameter to inform the AP that it
should conserve power to avoid brownout, and consider jumping to EC RW
to negotiate PD.
In addition, modify the existing CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
to allow power-up regardless of power level if a 15W+ charger is
attached, since there is a reasonable chance it may speak PD and provide
sufficient power to boot the AP.
BUG=chromium:537269
TEST=Manual on Glados. Set CHG_MW thresh to 20000, BAT_PCT to 50. Verify
that LIMIT_POWER charger param is set until Zinger negotiates to 20V. Also
veify that system can boot with Donette.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic963c82fea4ad10e8a5d7e476c5ce3e5ae525dad
Reviewed-on: https://chromium-review.googlesource.com/306774
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
ARM systems currently use SBS kernel driver which talks to the battery
through I2C passthu in the EC. Instead when asking for battery
information try getting it from the charge state machine first, and
then try the battery if charge state does not have the information.
This reduces latency by cutting out the battery response time.
BUG=chromium:484841
BRANCH=none
TEST=check that power_supply_info works properly on Jerry
Change-Id: If4da15ccabe412adc31fc94b189089ebb3e9265c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/307905
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Chell was still set to use W25Q64 instead of the W25X40 that is
actually on the board.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=successfully run "flash_ec --board=chell"
Change-Id: If21e5f9a00600c97d81d2bb2a8700801ae5c2fd6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308727
Reviewed-by: Shawn N <shawnn@chromium.org>
Add chell_pd to the STM32 list and the USBPD override list.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=successfully run "flash_ec --board=chell_pd"
Change-Id: Ic4ddbe51a0586c563211fd76f20a85428e565546
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308726
Reviewed-by: Shawn N <shawnn@chromium.org>
1. Implement deep doze mode for CONFIG_LOW_POWER_IDLE.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=test the following items in deep doze mode.
1. WUI interrupts wake-up OK. (For example, power button, lid,
uart rx, keyboard ksi, and so on)
2. LPC access interrupt wake-up OK.
3. Enabled Hook debug, no warning message received (48hrs).
Change-Id: I8702a112632cb6c1c0fa75d682badf272130a7d4
Reviewed-on: https://chromium-review.googlesource.com/307060
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If PD MCU crashes, it will go back to RO code and stay there
until the next AP boot. So, if EC detects PD has crashed, then
EC should panic reboot with debug message that it detected
a PD crash.
PD MCU crash is detected by EC by seeing the PD MCU transition
from RW to RO, without it setting the flag that it got there
from a sysjump.
This CL also makes minor changes to oak_pd and glados_pd board.c
files to make them identical, other than the few minor real
differences between them.
BUG=none
BRANCH=none
TEST=tested on glados using pdcmd console command on EC to test
sysjumps and reboots:
sysjump to RW: pdcmd 0xd2 0 2 0
sysjump to RO: pdcmd 0xd2 0 1 0
cold reboot: pdcmd 0xd2 0 4 0
Verified that PD can jump back and forth between RO and RW
without EC panicing. Verified that if PD MCU is in RW and
reboots, then the EC will panic and print 'PD crash'. Verify
if PD MCU reboots while in RO, without ever going to RW first,
then EC does not panic.
Change-Id: Id3191f4005e70a6c61a9322bf535b4374e85eb9a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308586
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Remove unnecessary 250ms delay in USB PD phy init
BUG=none
BRANCH=none
TEST=test on glados and samus. verify we negotiate with
zinger after EC or PD reboots.
Change-Id: I561e41fb0b8bbfeacdd7d6a9ceaf67a1606f65e5
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308535
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Modify the former workaround for board revisions missing an external
pull-up to 1.8V on EN_PP3300 :
the 100kOhm resistor between GPE13 and EN_PP3300 is still stuffed even
on boards which don't need the workaround, so tri-state the pin to avoid
driving the net.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:46799
TEST=probed EN_3300 voltage level.
Change-Id: I48f2b2fa9a716cdbe07fbc8a006ba4d3fcfaa63d
Reviewed-on: https://chromium-review.googlesource.com/307868
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 53e49d6d6541183349bb7267fa5ec2b1db250d99)
Reviewed-on: https://chromium-review.googlesource.com/308514
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
When ALS is enabled, if light is around one threshold (say 40 lux),
the lightbar will flicker between readings.
Add a histeresis to prevent the flickering.
The current setting is:
setting ^
(dim) 2 | ------+---->---+
1 | +----<---+--->---+
(bright) 0 | +---<---+---------
+-------+--------+-------+--------> lux
20 40 60
BRANCH=smaug
BUG=chrome-os-partner:44400
TEST=check in a dark room (30~40 lux) there is no flickering.
Add unit test.
Change-Id: I4018e2c2ed764abf9c9ed28e2d50a3e94a7d5f75
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308205
Gyro and compass is suspended but still powered on.
Therefore they don't need to be reinitialized.
Note that their init() does not do much, most is done when
initializing the accelerometer part of the BMI160.
BRANCH=smaug
BUG=none
TEST=Check that Gyro: MS Done Init... message are not present
when powering up the system in a loop.
Change-Id: If92727830c32407df49213db46b1d5f1cb0369af
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308204
Reviewed-by: Alec Berg <alecaberg@chromium.org>
The port80 task has been removed recently and replaced with a timer
interrupt (CL:305591). Fix lars to match the new scheme.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I602ef1306b9889732e77cbb32753ca0286123e2b
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308450
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Add VCONN swap ability and accept VCONN_SWAP requests as long
as we have the ability to provide VCONN.
BUG=none
BRANCH=none
TEST=test on glados. ask for vconn swap and make sure vconn swap
is successful.
Change-Id: I7340e6253dcde4cdbe333a9622d7826e7ccbe6b4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308238
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
