Before this change uart_ec_interrupt and software watchdog
interrupt handler both had priority 0. Since UART IRQ number is
33, and software watchdog is 44, the UART interrupt handler
would have higher prority.
Fix this by increasing all interrupt handler priorities, leaving
the software watchdog handler alone on priority 0.
BRANCH=eve,poppy,fizz
BUG=b:76391320
TEST=Cherry-pick CL:979736 (causes a watchdog in UART interrupt
handler), check that panicinfo contains a sensible PC in r5
after reset.
Change-Id: I97f99af5192a4a9571854a4d3f7c48a4674d605e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/979738
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If an ITIM32 timeout event occurred during lpc_sib_wait_host_read_done()
and lpc_sib_wait_host_write_done() routines, in rare case, ec might have
a chance to gets stuck since ec's interrupts are disabled when CSWR/CSRD
bits are high forever. (Normally, CSWR/CSRD bits won't be always high.
These bits are high forever also means something wrong on LPC/eSPI
bus.)
In order to prevent this situation, the CL checks TO_STS bit of ITCTS
in these routines. If this bit is set, restoring ITIM32 preload counter
value to maximum value and processing overflow will be done by
force_time().
BRANCH=eve,fizz,poppy
BUG=b:76182199
TEST=No build errors for npcx series. Passed test command of CL 979389
on npcx_evb. No symptom occurred during warm reset stress test on
soraka.
Change-Id: Ic645f7c5a2a1e49a3c1f3d7e089dd66b4bb75ac6
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/979874
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
No one is using this method and it implies that all chipset should
support the RCIN# Virtual Wire if using eSPI. Only large core chips
use RCIN#; small core chips don't.
This method was introduced for skylake and has since been replaced
since CL:575947 was merged.
BRANCH=none
BUG=none
TEST=build all
Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/975904
The CONFIG_UART_HOST is supposed to be defined to the index of the UART we
want to use. It is not supposed to be defined as a boolean. Updated npcx
and all incorrect uses.
BRANCH=none
BUG=none
TEST=Added the following diff to ensure that everything still built:
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index 446baa842..826233744 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -897,6 +897,9 @@ static void lpc_init(void)
/* Initialize Hardware for UART Host */
#ifdef CONFIG_UART_HOST
+#if !CONFIG_UART_HOST
+#error "Fix me"
+#endif
/* Init COMx LPC UART */
/* FMCLK have to using 50MHz */
NPCX_DEVALT(0xB) = 0xFF;
Change-Id: Ia46c7cb86c6040a5c75dddf23d5ccd8e33210581
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/949308
Reviewed-by: Randall Spangler <rspangler@chromium.org>
According to Nuvoton datasheet, when SHM windows are in IO mode, only the
bottom 16-bits of registers @ offset xF4 and xF8 are used.
"This register is ignored when WRAM1_IO bit in WIN_CFG register is set to
1 (LPC / eSPI Peripheral Channel I/O access with 16-bit address). This
register is set to its default value by Host Domain reset."
BRANCH=none
BUG=none
TEST=boot grunt and verify host communication still works.
Change-Id: I3e48ea1b09355eaf6967b9f7522bc3d35459b76b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/919006
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Since there is no KEYPROTO task on chromebox such as fizz and sion, lpc
driver doesn't declare KBC IBF/OBE ISRs for these events. If host put
data in ec's KBC input buffer unexpectedly, exception_panic() will be
executed in default_handler. Then we will see ec print
"=== PROCESS EXCEPTION: 29 ====== xPSR: 01000000 ===" message without
any hard fault and reset.
This CL fixed this symptom by turning off KBC if there is no KEYPROTO task.
We also run suspend stress test on fizz and no watchdog reset symptom
occurred.
BRANCH=none
BUG=b:72353876
TEST=No build errors. Run suspend stress test on fizz and no watchdog
reset occurred.
Change-Id: I4744fac0d6fb2628849c728d4860509434fa2cbb
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/899706
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
With the upcoming change to add a new command to get/set/clear host
events and masks, it seems to be the right time to bump up the host
events and masks to 64-bit. We are already out of available host
events. This change opens up at least 32 bits for new host events.
Old EC commands to operate on host events/masks will still deal with
lower 32-bits of the events/mask. On the other hand, the new command
being added will take care of the entire 64-bit events/masks. This
ensures that old BIOS and kernel versions can still work with the
newer EC versions.
BUG=b:69329196
BRANCH=None
TEST=make -j buildall. Verified:
1. hostevent set 0x4000 ==> Sets correct bit in host events
2. hostevent clear 0x4000 ==> Clears correct bit in host events
3. Kernel is able to query and read correct host event bits from
EC. Verified using evtest.
4. Coreboot is able to read correct wake reason from EC. Verified
using mosys eventlog list.
Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/770925
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a common hook handler on CHIPSET_RESUME to log port80 resume
message instead of duplicating the same code in all chip lpc_resume.
BUG=b:68669668
BRANCH=None
TEST=Verified that port80 resume is logged on S0ix and S3 resume.
Change-Id: I313692f5499717d0d8f62be2ba3b8566c46e4dde
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new LPC helper routine lpc_resume_clear_masks that can be used
to clear SCI, SMI and wake masks upon resume from S3. This is done to
mask the events until host explicitly unmasks them.
It also ensures that these masks do not get reset on resume from S0ix
where the host does not re-configure these masks.
BUG=b:68669668
BRANCH=None
TEST=Verified following:
1. make -j buildall
2. On resume from S0ix, SCI mask is not reset.
3. On resume from S3, SCI mask is reset and then set again by host request.
Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According npcx ec wake-up mechanism by espi VW events, the driver
needs to make sure the IE/WE bits in VWEVMSn and the VWUPD bit in
ESPIWE registers are both set. Or ec won't wakeup by VW signals until
the other wake-up events occured. (WE bit of VWEVMSn is introduced on
npcx7.)
In this CL, we turn on IE/WE bit in VWEVMSn registers during espi driver
initialization and toggle the bits of ESPIWE register for VW and general
events such as ESPI_RST and so on when ec turn on/off host interface's
interrupts to make sure ec can wake-up from deep idle by espi events in
time.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c
1000" to do stress test and no symptom occurred on poppy. Both warmboot
and coldboot stress test for 5 hours and no symptom occurred on poppy.
Change-Id: I853532508bf9da5f3abc39e20ab848e659ca5e26
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/725559
Reviewed-by: Amit Maoz <amit.maoz@nuvoton.corp-partner.google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Instead of duplicating the handling of host events and host event
masks in chip lpc drivers, add routines in common code to provide
basic functions like setting/getting of masks, setting/getting of
events and handling of masks transitions across sysjump.
BUG=None
BRANCH=None
TEST=make -j buildall. Verified following:
1. Event masks are correctly retained across sysjumps.
2. Wake from S3 works fine.
3. Wake from S0ix works fine.
4. SCI generated correctly.
Change-Id: Ie409f91b12788e4b902b2627e31ba5ce40ff1d27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/707771
Reviewed-by: Shawn N <shawnn@chromium.org>
In eSPI systems, when the host performs a data read from the Shared
Memory space, the returned data may be corrupted. This is a result of
the Core-to-Host access enable bit being toggled (by toggling CSAE bit
in SIBCTRL register) during an eSPI transaction. The bypass for this
symptom is to set CSAE bit to 1 during initialization and remove the
toggling of CSAE bit from other EC firmware code.
But keeping the CSAE bit at 1 forever also impacts the eSPI performance
a lots. When the core clock is stalled by sleep, deep sleep or wfi
instruction, the eSPI Peripheral Channel transaction is stalled if this
bit is set. The bypass for this symptom is to wake up the core by eSPI
peripheral channel transaction and let eSPI module handle the remaining
packet.
BRANCH=eve
BUG=b:64730183
TEST=No build errors for make buildall. Flash poppy ec image, make sure
it can boot to OS. Run "ectool version" over 100000 times, no error
occurs. Use following script "count=0; while :; do echo "---
iteration --- $count"; time flashrom -p ec -r ec.bin; sleep 5;
count=$((${count}+1)); done" to test eSPI performances over 1000
times. No errors occur and all tests' efficiency are the same as
removing CSAE bypass.
Change-Id: I1b9051c5a3d368a5917882d9d1c3bb00481a53ad
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/620301
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This reverts commit ddbfe690e2.
Reason for revert: Causes move cursor movements to be choppy, and device
to be very unresponsive during flashrom EC operations.
Original change's description:
> npcx: workaround the bug that SHM data read via eSPI may be corrupted
>
> In eSPI systems, when the Host performs a data read from the Shared
> Memory space, the returned data may be corrupted. This is a result of
> the Core-to-Host access enable bit being toggled (by toggling CSAE bit
> in SIBCTRL register) during an eSPI transaction.
>
> The workaround in this CL is to set CSAE bit to 1 during initialization
> and remove the toggling of CSAE bit from other EC firmware code.
> (i.e., let the CSAE bit be always 1.)
>
> BRANCH=none
> BUG=none
> TEST=No build errors for make buildall. Flash poppy ec image, make sure
> it can boot to OS. Run "ectool version" over 100000 times, no error
> occurs.
>
> Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe
> Signed-off-by: CHLin <CHLIN56@nuvoton.com>
> Reviewed-on: https://chromium-review.googlesource.com/590396
> Commit-Ready: Shawn N <shawnn@chromium.org>
> Tested-by: CH Lin <chlin56@nuvoton.com>
> Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=b:64730183
TEST=flashrom -p ec -r ecr.bin, device still responsive.
Change-Id: Idaeef2707df990b2441a77a15807698d41018449
Reviewed-on: https://chromium-review.googlesource.com/618366
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In eSPI systems, when the Host performs a data read from the Shared
Memory space, the returned data may be corrupted. This is a result of
the Core-to-Host access enable bit being toggled (by toggling CSAE bit
in SIBCTRL register) during an eSPI transaction.
The workaround in this CL is to set CSAE bit to 1 during initialization
and remove the toggling of CSAE bit from other EC firmware code.
(i.e., let the CSAE bit be always 1.)
BRANCH=none
BUG=none
TEST=No build errors for make buildall. Flash poppy ec image, make sure
it can boot to OS. Run "ectool version" over 100000 times, no error
occurs.
Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/590396
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Once ec receives LRESET/PLTRST on eSPI mode, both WUI57 of table 0 and
WUI15 of table 2 will be issued at the same time. We don't need two WUI
sources to indicate LRESET/PLTRST event on eSPI mode. This CL removes
initialization of LRESET/PLTRST of WUI57 of table 0 in lpc_init() for eSPI.
BUG=b:35954584
BRANCH=None
TEST=Verified that no more watchdog resets are seen on poppy.
Change-Id: Ib35b574d937c40d417ac707296ec080fd0244cf8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450022
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Setting HICTRL.FW_OBF clears the HIKMST.OBF and STATUS.OBF flags but it
does not deassert IRQ1 when already asserted. To make sure IRQ1 will
also be deasserted need to emulate a host read.
Modified drivers:
1. lpc.c: emulate a host read to clear OBF and deasserted IRQ1.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; Run FAFT items related to Power on/off, reboot,
and keyboard on Wheatley.
Change-Id: Ibf0ff3b8a4eeece853916e4e19d67fcc7ae2e989
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/419909
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since ec doesn't support old-style host command, this CL removes
unsupported parts in npcx's lpc driver and lets the hand-shaking
mechanism between host and ec as easy as possible. It makes sure only
following conditions that ec can clear processing bit of host command.
1. Received LRESET signal.
2. In lpc_init() initialization function caused by sysjump.
3. If command is valid, it will be cleared in lpc_send_response_packet()
called by host command task.
4. If command is invalid, it will be cleared in lpc_send_response()
after the response package is ready.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=wheatley; do stress test on wheatley.
Change-Id: I53d17fd9e09b7fb080e4bf71437392bf43db6258
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/422707
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There's a small period between ec cleared EC_LPC_CMDR_BUSY status bit
for sysjump and executed notify hook function to let lpc driver disable
lpc's interrupts. If ec received a new host command in this period,
EC_LPC_CMDR_BUSY status bit has chance not to be cleared since ec
already jumped to the the other region. In case ec and host enter
dead-lock loop, we need to clear it on lpc_init().
Since HIPMnST only can be reset by core domain reset, it's better to
clear EC_LPC_CMDR_BUSY status bit when LRESET asserted. It makes host
can reset host command mechanism if something wrong.
BRANCH=none
BUG=chrome-os-partner:60928
TEST=make BOARD=reef; pass the tests mentioned in issue #60928
Change-Id: I08ac0515cb2cfee277a7c7704d131574d928fb6b
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/419908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The original thought of setting LRESET_PLTRST_MODE to 1 is to remove the
need to reinitialize host module registers whenever LRESET# occurs in
order to save time when boot-up.
However, some of these registers will be reset by core domain reset. It
means every time LRESET is de-asserted, we need to initialize the host
setting again. Therefore, setting LRESET_PLTRST_MODE to 1 is unnecessary
and sometimes dangerous. If BIOS believes LRESET will reset ec's host
state machine to default but ec not, it will cause unexpected behavior.
Modified drivers:
1. lpc.c: allow LRESET/PLTRST generate host domain reset
BUG=chrome-os-partner:60211
BRANCH:none
TEST=make buildall. run "dut-control pwr_button:press; sleep 11; dut-control
pwr_button:release; sleep 7; dut-control pwr_button:press; sleep 1;
dut-control pwr_button:release". Verify keyboard works normally.
Change-Id: I94d428cde69f828468547c44844983f25686ea04
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/417745
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear
the wake masks when the SMI is invoked. For S0ix, EC sets and clears
the wake mask via this patch.
These functions are directly invoked from the state machine transition
states. During S0ix entry, the wake mask for lid open is enabled.
During S0ix exit, the wake mask for lid open is cleared. All pending
events are also cleared.
BRANCH=none
BUG=chrome-os-partner:58740
TEST=test lidopen in S0ix
Change-Id: I398fdba2b9bba1f6caef46f8dc71c7de3b669d08
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/401070
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
When GPIOC6/GPIO76 are not selected as SMI/SCI function(ie. selected
as GPIO), the reading of SMIB/SCIB will be a fixed value. This means
it cannot reflect the actul SMI/SCI status. As a reault, use SET_BIT/
CLEAR_BIT macro to toggle SMIB/SCIB is not feasible. Firmware should
read the SMI/SCI status from VWEVSM(2) register before setting it.
This CL defines some macros to achieve it.
In the previous CL, SMI/SCI negative polarity is conditionally
disabled. However, the negative polarity is not used in current
firmware design. Set the SMI/SCI polarity as postive unconditionly by
default.
Modified drivers:
1. lpc.c: use macro NPCX_VW_SMI/NPCX_VW_SCI to generate Virtual wire.
use SMI/SCI postive polarity uncontionally by default.
2. register.h : define macro to handle SMI/SCI virtual wire.
BUG=chrome-os-partner:34346
BRANCH=none
TEST=make buildall; try hostevent on Wheatley and check virtual wire
signal is correct on logical analyzer.
Change-Id: Id4a7748addeaa3b35f280ff29f6fcd8a08b9894b
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/400161
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Prior x86 boards have had GPIO for toggling RCIN directly on the PCH,
although many likely had HW-assisted methods as well.
With eve we need to generate an eSPI Virtual Wire for RCIN, but in reality
software control over RCIN Virtual Wire is not available with the npcx EC,
so the legacy LPC interface for pulsing KBRST must be used instead as this
is the only way to generate RCIN.
This method will likely vary on different EC chips, but for skylake it
can just be abstracted into the LPC module.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=successful 'apreset warm' on eve EC console
Change-Id: I7f9e7544a72877f75d05593b5e41f2f09a50e1c9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400037
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The check for whether or not to send an SMI needs to check the
same status bit that it is using to indicate that it is going
to send an SMI. The SMIE bit is enabled in lpc_init() so it is
always set.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=shutdown with lid close event at developer screen
Change-Id: I9a0f34025c4fa11175fca7be34224ec680bffbef
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400033
Reviewed-by: Shawn N <shawnn@chromium.org>
In current FW implement, there are two ways to generate SMI/SCI:
(1) Controlled by GPIO module register.(#define CONFIG_SCI_GPIO)
(2) Controlled by PM module register.(#undef CONFIG_SCI_GPIO)
This CL fix for case(2):
In this case, these two dedicated pins(GPIOC6/GPIO76) are used
as SMI/SCI and must be enabled by pinmux. Set the related pinmux
at initial.
By default, the SMI/SCI polarity is negative. This means SMI/SCI
is inverted when writing to SMI/SCIB but not inverted when reading
from them(see Section 5.2.2, figure 61 in datasheet). It will cause
the code more complicated to implement. Disable negative polarity
at init.
Modified drivers:
1. lpc.c: set pinmux for dedicated SMI/SCI pins and disable the
negative polarity.
BUG=chrome-os-partner:34346
BRANCH=none
TEST=make buildall; try hostevent(lid switch) on Wheatley with
CONFIG_SCL_GPIO undefined.
Change-Id: Ia317e54deb6861d7189b3594bd7414b53408b933
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/396718
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Before performing a sysjump, ensure that:
1. LPC interrupts are disabled : Ensures interrupts are not taken until
next enable.
2. LPC window is closed by writing 0xfffffff8 to window base addresses:
Prevents any memory corruption by host.
BUG=chrome-os-partner:57642
BRANCH=None
TEST=Verfied that LPC communication works after sysjump to RW.
Change-Id: I7b7826b2544f1c94cfa9c96b6ac82bc3517b1820
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388755
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
1. interrupt enabling should be the last thing done when lpc_init
completes required intialization
2. memset to 0 of static uninitialized variables is not required. Remove
that.
BUG=chrome-os-partner:57642
BRANCH=None
TEST=Verified that LPC communication is fine after sysjump to RW.
Change-Id: Ib8891dccf2b301590ebca41b75680d954d88a4d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388752
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
BUG=chrome-os-partner:55583
BRANCH=none
TEST=verified OBF status is cleared during idle without event which
means kernel driver waited for the BUSY bit and read the data.
Change-Id: I79357fea5483fe7a175c60f54235926e105ec832
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/373043
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Following steps need to be followed for SCI/SMI generation:
1. If automatic mode is being used, set SCIE/SMIE bit in HIPMIE register
during lpc_init. This step needs to be performed only once.
2. If SCI/SMI generation is required, set ST1/ST2 bit in HIPMST register
during update_host_event_status.
3. In lpc_generate_sci/smi, if automatic mode is being used, set
SCIB/SMIB bit in HIPMIC register.
BUG=chrome-os-partner:55489
BRANCH=None
TEST=lidclose behavior verified in kernel.
Change-Id: Ib6e0ee32bc06a8c51297010ac4843a7de45a99bd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/371059
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Add espi driver for x86-based platform which support espi interface such
as skylake and so on.
Added source:
1. espi.c: Add drivers which supports the utilities of peripheral and
virtual-wire channels so far.
2. espi.h: Add espi virtual-wire declaration for power sequence FW.
Modified sources:
1. lpc.c: Add interrupts and initialization steps for espi.
2. gpio.c: Add interrupt handler of espi reset.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
Change-Id: Ie80afe79d85aba47fc0b72898a8374c2898ec114
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/366181
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Our UART interrupt must be able to preempt our SHI_CS interrupt,
otherwise console input may be lost. Adjust our relative IRQ priorities
to accommodate this.
BUG=chrome-os-partner:55920
BRANCH=None
TEST=Run `echo "kbpress 11 4 1" > /dev/pts/17` on kevin 200 times from
the recovery screen, verify that all input is received by the EC.
Change-Id: I36203511f5883272287ac22d0704098fbd933758
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366622
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Different actions need to be taken on PLTRST_L depending on
if it is asserted or deasserted. The vstore module needs to
reset its locks when PLTRST_L is asserted (host is in reset).
The interrupt was previously on occurring on a deassertion of
PLTRST_L (rising edge). That's not conducive for handling
actions which are required for assertion (falling edge).
Lastly, fix the CONFIG_CHIPSET_RESET_HOOK logic to be
called when PLTRST_L is asserted.
BUG=chrome-os-partner:55471
BRANCH=None
TEST=Able to boot and reboot without getting vboot hash saving
errors. Also am able to see the assertion/deassertion messages
on the console.
Change-Id: I70eac3309a5876de775ec5c34dab2e9aa8bbb42c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362000
Reviewed-by: Shawn N <shawnn@chromium.org>
The bit IRQ11B of register HIIRQC is meaningful only when PM Channel 1
is in PC87570-Compatible. In previous commit, we deprecate use of
PC87570 mode but set the bit unintentionally. This will not cause any
bug but may make confused when reading the code.
Modified sources:
1. lpc.c: CLear IRQ11B in register HIIRQC.
BUG=chrome-os-partner:34346
TEST=make buildall -j; verify on Wheatley
BRANCH=none
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Change-Id: I594222c29557add847a1f689859fdf558d64fdd3
Reviewed-on: https://chromium-review.googlesource.com/358536
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
In NPCX5m5g/NPCX5m6g, PM channel 1 can support both
PC87570-Compatible and enhcnced mode. In next generation of chip,
only enhanced mode will be supported. Set the enhanced mode as
default in the firmware to support all gereration of chips.
BUG=chrome-os-partner:34346
TEST=make buildall -j; verify on Wheatley
BRANCH=none
Change-Id: Ide9e17a1fe8a0d2bfdc33efe2336a10702660679
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/357752
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
add optional chipset specific function to check if PLTRST# is valid
BUG=chrome-os-partner:52656
BRANCH=none
TEST=make buildall, able to boot to OS on amenia
Change-Id: I7a2747c4f77f50393c3250c2ab0e1625e64e5a41
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/341732
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously calls to hook_call_deferred were passed the function to call,
which was then looked up in the .rodata.deferred section with a linear
search. This linear search can be replaced with a subtract by passing
the pointer to the deferred_data object created when DECLARE_DEFERRED
was invoked.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
CQ-DEPEND=CL:*255812
TEST=make buildall -j
Change-Id: I951dd1541302875b102dd086154cf05591694440
Reviewed-on: https://chromium-review.googlesource.com/334315
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
EC clears the SCI/SMI/Wake masks in the resume sequence for S3
and S0ix. This works in the S3 case because Coreboot reprograms
the masks after EC. But in S0ix, these masks stay cleared forever.
This means that no further events are sent to the host.
This patch conditionally clears the masks only in the S3 transition.
BRANCH=glados
BUG=chrome-os-partner:48834
TEST=hostevent in EC console before and after S0ix to ensure SCI masks
are preserved
Change-Id: I23751680788ee7a239e321309a1334d37adc4f43
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/320191
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Fixed the bug that some of DP80's data is skipping if the speed of writing
by host is high. The solution is grabbing all data and sending them to UART
until FIFO of DP80 is empty in ISR.
Modified sources:
1. lpc.c: Fixed the bug that some of DP80's data is skipping.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ie53a5c7f0a80a1f836b571a00871cb57b42c87db
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/326931
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There are hooks for chipset power sequencing but not one to indicate
that the system has reset at runtime. Add a hook for this and
implement for lm4 and mec1322. The hook is notified on any platform
reset, including those that happen on the way into S3/S5 state.
There is a new config variable added because the hook is notified in
the interrupt handler and needs a deferrable function that needs to
be added to every board.
BUG=chrome-os-partner:46049
BRANCH=none
TEST=tested on glados and samus
Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315221
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Set alternative pin from GPIO to CLKRUN if SERIRQ is under quiet mode
Once we need LCLK, CLKRUN will pull low automatically.
Modified drivers:
1. lpc.c.: enable CLKRUN functionality for SERIRQ no matter continuous or
quiet mode.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I58b11340833b26bc64bfe499272fd3b319b33202
Signed-off-by: CHLin <chlin56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/314971
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
SERIRQ bug:
PMC1/2 share the same IRQ number 1 with default setting. Enable it will
influence 8042 protocols since KBC has no data but IRQ 1 is issued by
PMC.
AC detection bug:
GPIO definitions between AC_PRESENT and ACOK mismatched. AC_PRESENT will
always
be high even we don't plug the adaptor.
Modified drivers:
1. lpc.c: Remove enabling SERIRQ for PMC1/2 and disable IRQ12 for Mouse.
2. config_flash_layout.h: Modified for adjusting RAM size.
3. gpio.inc: Modified GPIO definitions for AC issue
4. board.h: Modified for adjusting RAM size and add support for ACC
5. board.c: Add support for ACC and adjust ADC max value
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ib330ef4078e4b06f1c01a2a6316e468b43d7a8d9
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/311933
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Modified i2c driver into controllers and ports to support I2C0 port 0/1 at
the same time.
Modified drivers:
1. i2c.c: Support i2c controller mechanism and fixed bug for i2c_raw functions
used by i2c_wedge and i2c_unwedge.
2. gpio.c: Fixed bug for gpio_alt_sel since wrong type of func.
3. lpc.c: Fixed bug for port80. Since disabling SUPPORT_P80_SEG, we should
replace GLUE_SDP0/1 with DP80BUF.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I9919269e4f5e795d9ceb8a4cd2c39abbd7bb6b1a
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/294015
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Fixed bug during polling port 0x204 by BIOS.
We should set processing flag before reading command byte in ISR to prevent
EC_LPC_STATUS_FROM_HOST and EC_LPC_STATUS_PROCESSING bits are both low.
Modified drivers:
1. gpio.c: Add LRESET ISR.
2. lpc.c: Fixed bug during polling port 0x204 by BIOS.
3. flash_ec: Reset ec before flashing ec
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I8e557f2e2be41a7a9d40c03c775313b12668f283
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/291210
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Add ECST tool to modify the header used by npcx booter.
Modified drivers:
1. i2c.c: Modify for i2c_port design.
2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue.
3. hwtimer.c: Fixed bug whcih event expired time is behide current timer.
4. lpc.c: Add intializing host settings after pltrst is deasserted.
5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle
when gpio is any-edge trigger mode.
6. task.c: Add workaround method for hard fault issue.
7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE
8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO
9. lpc.c: fixed obe interrupt bug during 8042 initialization
10.Adjust path of flat files for new Makefile rules
11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/284036
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
